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W83627DHG WINBOND LPC I/O
Note: This document is for UBC, UBE and UBF version except specified descriptions
Date : April 10, 2007
Version : 1.4
W83627DHG
Data Sheet Revision History
PAGES DATES VERSION WEB VERSION MAIN CONTENTS
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12/15/2005 02/22/2006
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1. 1. 1. 2. 3. 4. 5. 6. 7. 1. 2. 3. 4.
First published version. Add descriptions of the registers, functions,, AC/DC timing, and top marking Revise Table 8.1 and the timing chart of section 10.3.1 Add registers for AMDSI at LDB, CRF5h,CRF6h and F7h(Bank1) Swap LDB, CRF2h bit 0 and bit 1. Modify the default values for LDA, CRFEh Modify the descriptions of LD9, CR30h bit 0 and CRF7h bit 4. Remove LDA, CRE9h bit4 ~ 3 Swap LDC, CRE0h bit3~0 and CRE5h bit7~4 Add FDC, UART, Parallel Port and KBC interface descriptions Remove all the descriptions about AMDSI Modify the diagrams and descriptions for Current Mode Add two control bits for the selections of SYSFANOUT and CPUFANOUT0 output type at CR[24h] Remove the description of the internal pulled-up resistor of Parallel Port Modify the definitions of edge/level and enable/disable debounce circuit of GP30, GP31 and GP35 Modify the descriptions of LD7, CRF7h and LD9, CRE6h ~ CRE9h Remove the remaining descriptions about AMDSI in datasheet ver.0.4 Add a note for Index# of FDC Interface and pin 83(GP42) of Serial Port & Infrared Port Interface in Pin Description Reserve the bit 7 of LD0, CRF0h Modify the descriptions of TRAK0#, WP#, RDATA# and DSKCHG# of FDC Interface Modify the descriptions for strapping pins: HEFRAS, PENROM, PENKBC and EN_GTL Modify the DC spec. Remove the note and renew the descriptions for Index# of FDC Interface. Correct the descriptions of HM Device Bank 0, CR[12h] bit0. Add two control bits for AUXFANOUT and CPUFAOUT1 output type selection. Add a new bit at LDC, CR[E8h] bit 1 for more PECI
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03/15/2006
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05/05/2006
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5. 6. 7.
8. Correct typos and grammatical mistakes 5
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
WEB VERSION
PAGES
DATES
VERSION
MAIN CONTENTS
5. 1.
clock selection. Modify the default values of HM Device Bank 0, CR[43h] bit 5,0 and CR[46h] bit 2~1. Add new chapters for Serial Peripheral Interface, Configuration Register Access Protocol, Power Management, Serialized IRQ, Watchdog Timer VID Inputs and Outputs, and PCI Reset Buffers. Update the feature lists of the W83627DHG in Chapter 2 Features. Add descriptions of PECI and SST and a table of SMBus in Chapter 5 Pin Description. Add new sections of Caseopen and Beep Alarm Function in Chapter 7 Hardware Monitor. Add Clock Input Timing, PECI & SST Timing, and SPI Timing in Chapter 21 Specifications. Remove sections 9.4 and 9.5 (EXTFDD and EXT2FDD). Modify the descriptions of Hardware Monitor Device, Bank 0, Index 59h, bits(6..4). Add a beep control bit for VIN4 at Hardware Monitor Device, Bank 0, Index 57h, bit6. Remove status bit of PME# status of MIDI IRQ event at Logical Device A, CRF4, bit 1. Remove control bit of enable/disable PME# of MIDI at Logical Device A, CRF7, bit 1. Modify the descriptions of Tape Drive Register in Chapter 10 Floppy Disk Controller. Correct the description of Digital Input Register, bit (6-4) in Chapter 10 Floppy Disk Controller. Remove the description of "MR pin" in Digital Output Register in Chapter 10 Floppy Disk Controller. Adapt "Serial Flash Interface" to "Serial Peripheral Interface". Modify "Absolute Maximum Ratings" in Chapter 21 Specifications. Remove "VDD is 5V 10% tolerance" from the description of DC Characteristics in Chapter 21 Specifications.
2. 3. 4. 5. 6. 7. 8. N.A. 09/29/2006 0.6 N.A. 9. 10. 11. 12. 13. 14. 15. 16.
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17. Update "S5c o l d state" to "S5 state. 18. Remove the section of "AT Interface" in Chapter
10 Floppy Disk Controller. 9
N.A. 10/05/2006 1.0 N.A. 1. 1. Update AC Timing parameters and waveforms. Update Table 9.1 and Table 9.2 in Chapter 9 Serial Peripheral Interface Update CR2Ah in Chapter 20 Configuration Register Modify CR24h bit 0 to reserved
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12/12/2006
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Publication Release Date: Aug, 22, 2007 Version 1.4
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WEB VERSION
PAGES
DATES
VERSION
MAIN CONTENTS
4. 5.
Use "Tbase" instead of "TControl" Add the pins, registers description and AC timing for new ACPI function - VSBGATE#, ATXPGD, FTPRST, PWROK2 and SUSC# Modify the description for VSBGATE#, ATXPGD, FTPRST. Revise the definition for Logical Device A, CR[E5h] bit 0. Add new section of PWROK Generation in Chapter 14 Power Management Event. Add new timing of VSBGATE# in Chapter 21 Specifications. Modify the description of CR[2Ah], bits [7:4]. Modify the "t1" timing of RSMRST#. Modify the descriptions of 7.7.2 OVT# Interrupt Mode. Modify the "t3" and "t4" timing in Table 14.4 and section 21.3.3 Add a new DC spec. of RSMRST# PWROK for UBF version (In section 14.3 and 14.4) Add LPC Timing in section 21.4 Remove redundant Power on/off and LRESET# Timing Modify LPC Timing in section 21.4
1. 2. 3.
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4. 5. 6. 7. 8. 1.
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03/28/2007
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04/10/2007
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Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
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Publication Release Date: Aug, 22, 2007 Version 1.4
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Table of Contents1. 2. 3. 4. 5. GENERAL DESCRIPTION ............................................................................................................... 1 FEATURES....................................................................................................................................... 2 BLOCK DIAGRAM ............................................................................................................................ 5 PIN LAYOUT..................................................................................................................................... 6 PIN DESCRIPTION .......................................................................................................................... 8 5.1 LPC Interface .......................................................................................................................... 9 5.2 FDC Interface .......................................................................................................................... 9 5.3 Multi-Mode Parallel Port........................................................................................................ 10 5.4 Serial Port & Infrared Port Interface...................................................................................... 12 5.5 KBC Interface ........................................................................................................................ 14 5.6 Serial Peripheral Interface..................................................................................................... 14 5.7 Hardware Monitor Interface................................................................................................... 15 5.8 PECI Interface ....................................................................................................................... 17 5.9 SST Interface ........................................................................................................................ 17 5.10 Advanced Configuration and Power Interface ...................................................................... 17 5.11 General Purpose I/O Port...................................................................................................... 18
5.11.1 5.11.2 5.11.3 5.11.4 5.11.5 5.11.6 5.11.7 5.11.8 SMBus Interface ....................................................................................................................18 GPIO Power Source...............................................................................................................18 GPIO-2 Interface ....................................................................................................................19 GPIO-3 Interface ....................................................................................................................20 GPIO-4 Interface ....................................................................................................................20 GPIO-5 Interface ....................................................................................................................21 GPIO-6 Interface ....................................................................................................................21 GPIO-4 with WDTO# / SUSLED Multi-function ......................................................................22
5.12 Particular ACPI Function pins - both for UBE and UBF Version Only ................................. 22 5.13 POWER PINS ....................................................................................................................... 23 6. CONFIGURATION REGISTER ACCESS PROTOCOL ................................................................. 24 6.1 Configuration Sequence ........................................................................................................... 25
6.1.1 6.1.2 6.1.3 6.1.4 Enter the Extended Function Mode........................................................................................25 Configure the Configuration Registers ...................................................................................25 Exit the Extended Function Mode ..........................................................................................26 Software Programming Example ...........................................................................................26
7. HARDWARE MONITOR ................................................................................................................. 28 7.1 General Description .............................................................................................................. 28 7.2 Access Interfaces.................................................................................................................. 28
7.2.1 7.2.2 LPC Interface .........................................................................................................................29 I2C interface ...........................................................................................................................30 Voltages Over 2.048 V or Less Than 0 V...............................................................................31 Voltage Detection...................................................................................................................32
7.3
Analog Inputs ........................................................................................................................ 31
7.3.1 7.3.2
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7.3.3 Temperature Sensing.............................................................................................................32 Command Summary ..............................................................................................................34 Combination Sensor Data Format..........................................................................................35
7.4
SST Command Summary ..................................................................................................... 34
7.4.1 7.4.2
7.5 7.6
PECI ...................................................................................................................................... 36 Fan Speed Measurement and Control.................................................................................. 39
7.6.1 7.6.2 7.6.3 Fan Speed Measurement.......................................................................................................39 Fan Speed Control .................................................................................................................40 SMART FANTM Control ..........................................................................................................41 SMI# Interrupt Mode ..............................................................................................................50 OVT# Interrupt Mode .............................................................................................................53 Caseopen Detection...............................................................................................................54 BEEP Alarm Function ............................................................................................................55
7.7
Interrupt Detection................................................................................................................. 50
7.7.1 7.7.2 7.7.3 7.7.4
8. HARDWARE MONITOR REGISTER SET ..................................................................................... 56 8.1 Address Port (Port x5h)......................................................................................................... 56 8.2 Data Port (Port x6h) .............................................................................................................. 56 8.3 SYSFANOUT PWM Output Frequency Configuration Register - Index 00h (Bank 0).......... 57 8.4 SYSFANOUT Output Value Select Register - Index 01h (Bank 0)....................................... 57 8.5 CPUFANOUT0 PWM Output Frequency Configuration Register - Index 02h (Bank 0) ....... 58 8.6 CPUFANOUT0 Output Value Select Register - Index 03h (Bank 0) .................................... 59 8.7 FAN Configuration Register I - Index 04h (Bank 0) .............................................................. 59 8.8 SYSTIN Target Temperature Register/ SYSFANIN Target Speed Register - Index 05h (Bank 0)..................................................................................................................................................60 8.9 CPUTIN Target Temperature Register/ CPUFANIN0 Target Speed Register - Index 06h (Bank 0)........................................................................................................................................... 61 8.10 Tolerance of Target Temperature or Target Speed Register - Index 07h (Bank 0).............. 61 8.11 SYSFANOUT Stop Value Register - Index 08h (Bank 0) ..................................................... 62 8.12 CPUFANOUT0 Stop Value Register - Index 09h (Bank 0)................................................... 62 8.13 SYSFANOUT Start-up Value Register - Index 0Ah (Bank 0) ............................................... 63 8.14 CPUFANOUT0 Start-up Value Register - Index 0Bh (Bank 0) ............................................. 63 8.15 SYSFANOUT Stop Time Register - Index 0Ch (Bank 0)...................................................... 64 8.16 CPUFANOUT0 Stop Time Register - Index 0Dh (Bank 0) ................................................... 64 8.17 Fan Output Step Down Time Register - Index 0Eh (Bank 0)................................................ 65 8.18 Fan Output Step Up Time Register - Index 0Fh (Bank 0)..................................................... 65 8.19 AUXFANOUT PWM Output Frequency Configuration Register - Index 10h (Bank 0) ......... 66 8.20 AUXFANOUT Output Value Select Register - Index 11h (Bank 0)....................................... 66 8.21 FAN Configuration Register II - Index 12h (Bank 0) ............................................................. 67 8.22 AUXTIN Target Temperature Register/ AUXFANIN0 Target Speed Register - Index 13h (Bank 0)........................................................................................................................................... 68 8.23 Tolerance of Target Temperature or Target Speed Register - Index 14h (Bank 0).............. 69 8.24 AUXFANOUT Stop Value Register - Index 15h (Bank 0) ..................................................... 69 8.25 AUXFANOUT Start-up Value Register - Index 16h (Bank 0)................................................ 70 Publication Release Date: Aug, 22, 2007 Version 1.4
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W83627DHG
8.26 AUXFANOUT Stop Time Register - Index 17h (Bank 0) ...................................................... 70 8.27 OVT# Configuration Register - Index 18h (Bank 0) .............................................................. 71 8.28 Reserved Registers - Index 19h ~ 1Fh (Bank 0) .................................................................. 71 8.29 Value RAM Index 20h ~ 3Fh (Bank 0).............................................................................. 71 8.30 Configuration Register - Index 40h (Bank 0)......................................................................... 73 8.31 Interrupt Status Register 1 - Index 41h (Bank 0) .................................................................. 73 8.32 Interrupt Status Register 2 - Index 42h (Bank 0) .................................................................. 74 8.33 SMI# Mask Register 1 - Index 43h (Bank 0) ......................................................................... 75 8.34 SMI# Mask Register 2 - Index 44h (Bank 0) ......................................................................... 75 8.35 Reserved Register - Index 45h (Bank 0)............................................................................... 75 8.36 SMI# Mask Register 3 - Index 46h (Bank 0) ......................................................................... 75 8.37 Fan Divisor Register I - Index 47h (Bank 0).......................................................................... 76 8.38 Serial Bus Address Register - Index 48h (Bank 0) ............................................................... 77 8.39 CPUFANOUT0/AUXFANOUT monitor Temperature source select register - Index 49h (Bank 0).................................................................................................................................................... 77 8.40 CPUFANOUT1 Monitor Temperature Source Select Register - Index 4Ah (Bank 0)........... 78 8.41 Fan Divisor Register II - Index 4Bh (Bank 0) ........................................................................ 79 8.42 SMI#/OVT# Control Register - Index 4Ch (Bank 0).............................................................. 79 8.43 FAN IN/OUT Control Register - Index 4Dh (Bank 0) ............................................................ 80 8.44 Register 50h ~ 5Fh Bank Select Register - Index 4Eh (Bank 0) .......................................... 81 8.45 Winbond Vendor ID Register - Index 4Fh (Bank 0) .............................................................. 81 8.46 Reserved Register - Index 50h ~ 55h (Bank 0) .................................................................... 82 8.47 BEEP Control Register 1 - Index 56h (Bank 0)..................................................................... 82 8.48 BEEP Control Register 2 - Index 57h (Bank 0)..................................................................... 83 8.49 Chip ID - Index 58h (Bank 0)................................................................................................. 84 8.50 Diode Selection Register - Index 59h (Bank 0)..................................................................... 84 8.51 Reserved Register - Index 5Ah ~ 5Ch (Bank 0) ................................................................... 85 8.52 VBAT Monitor Control Register - Index 5Dh (Bank 0) .......................................................... 85 8.53 Critical Temperature and Current Mode Enable Register - Index 5Eh (Bank 0) .................. 86 8.54 Reserved Register - Index 5Fh (Bank 0) .............................................................................. 87 8.55 CPUFANOUT1 PWM Output Frequency Configuration Register - Index 60h (Bank 0) ....... 87 8.56 CPUFANOUT1 Output Value Select Register - Index 61h (Bank 0) .................................... 87 8.57 FAN Configuration Register III - Index 62h (Bank 0) ............................................................ 88 8.58 Target Temperature Register/CPUFANIN1 Target Speed Register - Index 63h (Bank 0) ... 89 8.59 CPUFANOUT1 Stop Value Register - Index 64h (Bank 0)................................................... 89 8.60 CPUFANOUT1 Start-up Value Register - Index 65h (Bank 0) ............................................. 90 8.61 CPUFANOUT1 Stop Time Register - Index 66h (Bank 0) .................................................... 90 8.62 CPUFANOUT0 Maximum Output Value Register - Index 67h (Bank 0)............................... 91 8.63 CPUFANOUT0 Output Step Value Register - Index 68h (Bank 0) ....................................... 91 8.64 CPUFANOUT1 Maximum Output Value Register - Index 69h (Bank 0)............................... 92 8.65 CPUFANOUT1 Output Step Value Register - Index 6Ah (Bank 0)....................................... 92 8.66 SYSFANOUT Critical Temperature register - Index 6Bh (Bank 0) ....................................... 93
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Publication Release Date: Aug, 22, 2007 Version 1.4
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8.67 CPUFANOUT0 Critical Temperature Register - Index 6Ch (Bank 0) ................................... 93 8.68 AUXFANOUT Critical Temperature Register - Index 6Dh (Bank 0) ..................................... 93 8.69 CPUFANOUT1 Critical Temperature Register - Index 6Eh (Bank 0) ................................... 94 8.70 CPUTIN Temperature Sensor Temperature (High Byte) Register - Index 50h (Bank 1)...... 94 8.71 CPUTIN Temperature Sensor Temperature (Low Byte) Register - Index 51h (Bank 1) ...... 95 8.72 CPUTIN Temperature Sensor Configuration Register - Index 52h (Bank 1)........................ 95 8.73 CPUTIN Temperature Sensor Hysteresis (High Byte) Register - Index 53h (Bank 1) ......... 96 8.74 CPUTIN Temperature Sensor Hysteresis (Low Byte) Register - Index 54h (Bank 1) .......... 96 8.75 CPUTIN Temperature Sensor Over-temperature (High Byte) Register - Index 55h (Bank1)97 8.76 CPUTIN Temperature Sensor Over-temperature (Low Byte) Register - Index 56h (Bank 1)..................................................................................................................................97 8.77 AUXTIN Temperature Sensor Temperature (High Byte) Register - Index 50h (Bank 2)...... 98 8.78 AUXTIN Temperature Sensor Temperature (Low Byte) Register - Index 51h (Bank 2)....... 98 8.79 AUXTIN Temperature Sensor Configuration Register - Index 52h (Bank 2) ........................ 98 8.80 AUXTIN Temperature Sensor Hysteresis (High Byte) Register - Index 53h (Bank 2).......... 99 8.81 AUXTIN Temperature Sensor Hysteresis (Low Byte) Register - Index 54h (Bank 2) .......... 99 8.82 AUXTIN Temperature Sensor Over-temperature (High Byte) Register - Index 55h (Bank 2).................................................................................................................................................. 100 8.83 AUXTIN Temperature Sensor Over-temperature (Low Byte) Register - Index 56h (Bank 2).................................................................................................................................................. 100 8.84 Interrupt Status Register 3 - Index 50h (Bank 4) ................................................................ 101 8.85 SMI# Mask Register 4 - Index 51h (Bank 4) ....................................................................... 102 8.86 Reserved Register - Index 52h (Bank 4)............................................................................. 102 8.87 BEEP Control Register 3 - Index 53h (Bank 4)................................................................... 102 8.88 SYSTIN Temperature Sensor Offset Register - Index 54h (Bank 4) .................................. 103 8.89 CPUTIN Temperature Sensor Offset Register - Index 55h (Bank 4).................................. 103 8.90 AUXTIN Temperature Sensor Offset Register - Index 56h (Bank 4) .................................. 104 8.91 Reserved Register - Index 57h-58h (Bank 4) ..................................................................... 104 8.92 Real Time Hardware Status Register I - Index 59h (Bank 4).............................................. 104 8.93 Real Time Hardware Status Register II - Index 5Ah (Bank 4) ............................................ 105 8.94 Real Time Hardware Status Register III - Index 5Bh (Bank 4) ........................................... 106 8.95 Reserved Register - Index 5Ch ~ 5Fh (Bank 4).................................................................. 107 8.96 Value RAM 2 Index 50h-59h (Bank 5)............................................................................ 107 8.97 Reserved Register - Index 50h ~ 57h (Bank 6) .................................................................. 107 9. SERIAL PERIPHERAL INTERFACE............................................................................................ 108 9.1 Using the SPI Interface via the LPC ................................................................................... 108 10. FLOPPY DISK CONTROLLER..................................................................................................... 111 10.1 FDC Functional Description ................................................................................................ 111
10.1.1 10.1.2 10.1.3 10.1.4 10.1.5 FIFO (Data)..........................................................................................................................111 Data Separator.....................................................................................................................112 Write Precompensation........................................................................................................112 Perpendicular Recording Mode............................................................................................112 FDC Core.............................................................................................................................112
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Publication Release Date: Aug, 22, 2007 Version 1.4
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10.1.6 10.2.1 10.2.2 10.2.3 10.2.4 10.2.5 10.2.6 10.2.7 10.2.8 10.2.9 FDC Commands ..................................................................................................................113 Status Register A (SA Register) (Read base address + 0) ..................................................124 Status Register B (SB Register) (Read base address + 1) ..................................................126 Digital Output Register (DO Register) (Write base address + 2)..........................................128 Tape Drive Register (TD Register) (Read base address + 3) ..............................................128 Main Status Register (MS Register) (Read base address + 4) ............................................129 Data Rate Register (DR Register) (Write base address + 4) ...............................................129 FIFO Register (R/W base address + 5)................................................................................131 Digital Input Register (DI Register) (Read base address + 7) ..............................................133 Configuration Control Register (CC Register) (Write base address + 7)..............................134
10.2 Register Descriptions .......................................................................................................... 124
11. UART PORT ................................................................................................................................. 136 11.1 Universal Asynchronous Receiver/Transmitter (UART A, UART B)................................... 136 11.2 Register Description............................................................................................................ 136
11.2.1 11.2.2 11.2.3 11.2.4 11.2.5 11.2.6 11.2.7 11.2.8 11.2.9 UART Control Register (UCR) (Read/Write) ........................................................................136 UART Status Register (USR) (Read/Write)..........................................................................139 Handshake Control Register (HCR) (Read/Write)................................................................140 Handshake Status Register (HSR) (Read/Write) .................................................................140 UART FIFO Control Register (UFR) (Write only) .................................................................141 Interrupt Status Register (ISR) (Read only) .........................................................................142 Interrupt Control Register (ICR) (Read/Write) ......................................................................143 Programmable Baud Generator (BLL/BHL) (Read/Write) ....................................................143 User-defined Register (UDR) (Read/Write)..........................................................................144
12. PARALLEL PORT......................................................................................................................... 145 12.1 Printer Interface Logic ......................................................................................................... 145 12.2 Enhanced Parallel Port (EPP)............................................................................................. 146
12.2.1 12.2.2 12.2.3 12.2.4 12.2.5 12.2.6 12.2.7 12.3.1 12.3.2 12.3.3 12.3.4 12.3.5 12.3.6 12.3.7 12.3.8 12.3.9 Data Port (Data Swapper)....................................................................................................147 Printer Status Buffer.............................................................................................................147 Printer Control Latch and Printer Control Swapper ..............................................................147 EPP Address Port ................................................................................................................148 EPP Data Port 0-3 ...............................................................................................................148 EPP Pin Descriptions ...........................................................................................................149 EPP Operation .....................................................................................................................149 ECP Register and Bit Map ...................................................................................................151 Data and ecpAFifo Port........................................................................................................152 Device Status Register (DSR)..............................................................................................152 Device Control Register (DCR) ............................................................................................153 CFIFO (Parallel Port Data FIFO) Mode = 010......................................................................153 ECPDFIFO (ECP Data FIFO) Mode = 011 ..........................................................................153 TFIFO (Test FIFO Mode) Mode = 110 .................................................................................154 CNFGA (Configuration Register A) Mode = 111 ..................................................................154 CNFGB (Configuration Register B) Mode = 111 ..................................................................154
12.3 Extended Capabilities Parallel (ECP) Port.......................................................................... 150
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Publication Release Date: Aug, 22, 2007 Version 1.4
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12.3.10 12.3.11 12.3.12 12.3.13 12.3.14 12.3.15 ECR (Extended Control Register) Mode = all ......................................................................155 ECP Pin Descriptions...........................................................................................................156 ECP Operation.....................................................................................................................157 FIFO Operation ....................................................................................................................158 DMA Transfers.....................................................................................................................158 Programmed I/O (NON-DMA) Mode ....................................................................................158
13. KEYBOARD CONTROLLER ........................................................................................................ 159 13.1 Output Buffer ....................................................................................................................... 159 13.2 Input Buffer.......................................................................................................................... 159 13.3 Status Register.................................................................................................................... 160 13.4 Commands .......................................................................................................................... 160 13.5 Hardware GATEA20/Keyboard Reset Control Logic .......................................................... 162
13.5.1 13.5.2 KB Control Register .............................................................................................................162 Port 92 Control Register.......................................................................................................163
14. POWER MANAGEMENT EVENT ................................................................................................ 164 14.1 Power Control Logic............................................................................................................ 164
14.1.1 14.1.2 14.2.1 14.2.2 PSON# Logic .......................................................................................................................165 AC Power Failure Resume...................................................................................................166 Waken up by Keyboard events ............................................................................................167 Waken up by Mouse events.................................................................................................167
14.2 Wake Up the System by Keyboard and Mouse .................................................................. 167
14.3 Resume Reset Logic........................................................................................................... 168 14.4 PWROK Generation............................................................................................................ 169
14.4.1 The Relation among PWROK/PWROK2, ATXPGD and FTPRST# - both for UBE and UBF Version Only.......................................................................................................................................170
15. SERIALIZED IRQ.......................................................................................................................... 173 15.1 Start Frame ......................................................................................................................... 173 15.2 IRQ/Data Frame.................................................................................................................. 174 15.3 Stop Frame.......................................................................................................................... 175 16. WATCHDOG TIMER .................................................................................................................... 176 17. GENERAL PURPOSE I/O ............................................................................................................ 177 18. VID INPUTS AND OUTPUTS ....................................................................................................... 178 18.1 VID Input Detection ............................................................................................................. 178 18.2 VID Output Control.............................................................................................................. 178 19. PCI RESET BUFFERS ................................................................................................................. 179 20. CONFIGURATION REGISTER .................................................................................................... 180 20.1 Chip (Global) Control Register ............................................................................................ 180 20.2 Logical Device 0 (FDC) ....................................................................................................... 187 20.3 Logical Device 1 (Parallel Port)........................................................................................... 190 20.4 Logical Device 2 (UART A) ................................................................................................. 191 20.5 Logical Device 3 (UART B) ................................................................................................. 191 20.6 Logical Device 5 (Keyboard Controller) .............................................................................. 193
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20.7 Logical Device 6 (Serial Peripheral Interface)..................................................................... 194 20.8 Logical Device 7 (GPIO6) ................................................................................................... 195 20.9 Logical Device 8 (WDTO# & PLED) ................................................................................... 196 20.10 Logical Device 9 (GPIO2, GPIO3, GPIO4, GPIO5) ............................................................ 198 20.11 Logical Device A (ACPI)...................................................................................................... 202 20.12 Logical Device B (Hardware Monitor) ................................................................................. 210 20.13 Logical Device C (PECI, SST) ............................................................................................ 212 21. SPECIFICATIONS ........................................................................................................................ 216 21.1 Absolute Maximum Ratings ................................................................................................ 216 21.2 DC CHARACTERISTICS .................................................................................................... 216 21.3 AC CHARACTERISTICS .................................................................................................... 225
21.3.1 21.3.2 21.3.3 21.3.4 21.3.5 21.3.6 21.3.7 21.3.8 21.3.9 21.3.10 21.3.11 21.3.12 AC Power Failure Resume Timing .......................................................................................225 VSBGATE# Timing - for UBE and UBF Version Only .........................................................230 Clock Input Timing ...............................................................................................................231 PECI and SST Timing ..........................................................................................................232 SPI Timing ...........................................................................................................................233 SMBus Timing......................................................................................................................234 Floppy Disk Drive Timing .....................................................................................................235 UART/Parallel Port...............................................................................................................236 Parallel Port Mode Parameters ............................................................................................238 Parallel Port .........................................................................................................................239 KBC Timing Parameters ......................................................................................................248 GPIO Timing Parameters.....................................................................................................251
21.4 LPC Timing.......................................................................................................................... 253 22. TOP MARKING SPECIFICATION ................................................................................................ 254 23. PACKAGE SPECIFICATION ........................................................................................................ 255
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
1. GENERAL DESCRIPTION
The W83627DHG is a member of Winbond's Super I/O product line. This family features the LPC (Low Pin Count) interface. This interface is more economical than its ISA counterpart, in that it has approximately forty pins fewer, yet still provides as great performance. In addition, the improvement allows even more efficient operation of software, BIOS and device drivers. In addition to providing an LPC interface for I/O, the W83627DHG monitors several critical parameters in PC hardware, including power supply voltages, fan speeds, and temperatures. In terms of temperature monitoring, the W83627DHG adopts the Current Mode (dual current source) approach. The W83627DHG also supports the Smart Fan control system, including "SMART FANTM I and SMART FANTM III, which makes the system more stable and user-friendly. The W83627DHG supports four -- 360K, 720K, 1.2M, 1.44M, or 2.88M -- disk drive types and data transfer rates of 250 Kb/s, 300 Kb/s, 500 Kb/s,1 Mb/s, and 2 Mb/s. The disk drive adapter supports the functions of floppy disk drive controller (compatible with the industry standard 82077/ 765), data separator, write pre-compensation circuit, decode logic, data rate selection, clock generator, drive interface control logic, and interrupt and DMA logic. Such a wide range of functions integrated into one W83627DHG greatly reduces the number of required components to interface with floppy disk drives. The W83627DHG provides two high-speed serial communication ports (UARTs), one of which provides IR functions IrDA 1.0 (SIR for 1.152K bps). Each UART includes a 16-byte send/receive FIFO, a programmable baud rate generator, complete modem-control capability, and a processor interrupt system. Both UARTs support legacy speeds up to 115.2K bps as well as even higher baud rates of 230K, 460K, or 921K bps to support higher speed modems. The W83627DHG supports the PC-compatible printer port (SPP), the bi-directional printer port (BPP), the enhanced parallel port (EPP) and the extended capabilities port (ECP). The W83627DHG provides a bridge of the Low Pin Count interface to Serial Peripheral Interface (SPI) that supports up to 8M bits serial flash ROM. The W83627DHG provides flexible I/O control functions through a set of 40 general purpose I/O (GPIO) ports. These GPIO ports may serve as simple I/O ports or may be individually configured to provide alternative functions. The W83627DHG supports the SST (Simple Serial Transport) interface and Intel(R) PECI (Platform Environment Control Interface). The W83627DHG fully complies with the Microsoft(c) PC98, PC99 and PC2001 System Design Guides and meets the requirements of ACPI. The configuration registers inside the W83627DHG support mode selection, function enable and disable, and power-down selection. Furthermore, the configurable PnP features are compatible with the plug-and-play feature in Windows 95/98/2000/XPTM, making the allocation of the system resources more efficient than ever. One special characteristic of the Super I/O product line is the separation of the power supply in normal operation from that in standby operation. Please pay attention to the layout of these two power supplies to avoid short circuits. Otherwise, the feature will not function.
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
2. FEATURES
Meet LPC Spec. 1.01 Support LDRQ# (LPC DMA), SERIRQ (Serialized IRQ) Integrated hardware monitor functions Compliant with Microsoft PC98/PC99/PC2001 System Design Guide Support DPM (Device Power Management), ACPI (Advanced Configuration and Power Interface) Programmable configuration settings Single 24- or 48-MHz clock input Support selective pins of 5 V tolerance
General
FDC
Variable write pre-compensation with track-selection capability Support vertical recording format DMA-enable logic 16-byte data FIFOs Support floppy disk drives and tape drives Detect all overrun and underrun conditions Built-in address mark detection circuit to simplify the read electronics FDD anti-virus functions with software write protect and FDD-write enable signal (write data signal forced to be inactive) Support 3.5-inch or 5.25-inch floppy disk drives Compatible with industry standard 82077 360K / 720K / 1.2M / 1.44M / 2.88M formats 250K, 300K, 500K, 1M, 2M bps data transfer rate Support 3-mode FDD and its Windows driver
UART
Two high-speed, 16550-compatible UARTs with 16-byte send / receive FIFOs Fully programmable serial-interface characteristics: --- 5, 6, 7 or 8-bit characters --- Even, odd or no parity bit generation/detection --- 1, 1.5 or 2 stop-bit generation Internal diagnostic capabilities: --- Loop-back controls for communications link fault isolation --- Break, parity, overrun, framing error simulation Programmable baud rate generator allows division of clock source by any value from 1 to (2 -1) Maximum baud rate for clock source 14.769 MHz is up to 921K bps. The baud rate at 24 MHz is 1.5 M bps.
16
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
Parallel Port
Compatible with IBM parallel port Support PS/2-compatible bi-directional parallel port Support Enhanced Parallel Port (EPP) - Compatible with IEEE 1284 specification Support Extended Capabilities Port (ECP) - Compatible with IEEE 1284 specification Enhanced printer port back-drive current protection
Keyboard Controller
* * * * * * * * 8042-based keyboard controller Asynchronous Access to two data registers and one status register Software-compatible with 8042 Support PS/2 mouse Support Port 92 Support both interrupt and polling modes Fast Gate A20 and Hardware Keyboard Reset 6, 8, 12, or 16 MHz operating frequency
Hardware Monitor Functions
Smart Fan control system, supporting the functions of SMART FANTM I -- "Thermal CruiseTM" and "Speed CruiseTM" modes, and SMART FANTM III Programmable threshold temperature to speed fan fully while current temperature exceeds this threshold in the Thermal CruiseTM mode Three thermal inputs from the different combinations of remote thermistors, and the thermal diode output Support Current Mode (dual current source) temperature sensing method Nine voltage inputs (CPUVCORE, VIN[0..3] and 3VCC, AVCC , 3VSB, VBAT) Five fan-speed monitoring inputs Four fan-speed controls Dual mode for fan control (PWM and DC) Built-in case open detection circuit Programmable hysteresis and setting points for all monitored items Over-temperature indicator output Issue SMI#, OVT# to activate system protection Winbond Hardware DoctorTM support Eight VID inputs / outputs Provide I2C interface to read / write registers
Serial Peripheral Interface
Support up to 8M bits SPI Flash Memory with clock up to 33 MHz Support Mode 0 and Mode 3
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
Infrared
* * Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps Support SHARP ASK-IR protocol with maximum baud rate up to 57,600 bps
General Purpose I/O Ports
40 programmable general purpose I/O ports GPIO port 4 supports the optional functions of Watchdog Timer Out and Suspend LED Output GP30, GP31 and GP35 can distinguish whether the input pins undergo any transitions by reading the registers. All of the 3 GPIOs can assert PSOUT# or PME# to wake up the system if each of them undergoes any transition.
OnNow Functions
Keyboard Wake-Up by programmable keys Mouse Wake-Up by programmable buttons OnNow Wake-Up from all of the ACPI sleeping states (S1-S5)
Simple Serial TransportTM Interface
SST temperature and voltage Combination Sensor command support Support SST 0.9 Specification
PECI Interface
Support PECI 1.0 Specification Support 4 CPU addresses and 2 domains per CPU address
Package
128-pin QFP Pb-free/RoHS
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
3. BLOCK DIAGRAM
LRESET#, PCICLK, LFRAME#, LAD[3:0], LDRQ#, SERIRQ
LPC Interface
SST SCL SDA General-purpose I/O pins Hardware Monitor channel and Vref Keyboard/Mouse data and clock VID I/O pins Serial Peripheral Interface
SST Interface SMBus Interface
FDC
Floppy drive interface signals UARTA interface signals UARTB interface signals Infrared interface signals Printer port interface signals
UARTA UARTB IR
GPIO
HM PRT KBC ACPI VID SPI PECI Interface
PECI
W83627DHG
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Publication Release Date: Aug, 22, 2007 Version 1.4
4.
CPUTIN SYSTIN CPUDPECISB Vtt PECI NC NC AUXFANIN0 CPUFANIN0 SYSFANIN SST CPUFANOUT0 SYSFANOUT (FAN_SET)PLED BEEP/SO GP21/CPUFANIN1 GP20/CPUFANOUT1 VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
PIN LAYOUT
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
DRVDEN0 GP23/SCK INDEX# MOA# SMI#/OVT# DSA# AUXFANOUT DIR# STEP# WD# WE# 3VCC TRAK0# WP# RDATA# HEAD# DSKCHG# IOCLK GP22/SCE VSS PCICLK LDRQ# SERIRQ LAD3 LAD2 LAD1 LAD0 3VCC LFRAME# LRESET# SLCT PE BUSY ACK# PD7 PD6 PD5 PD4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
3VCC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
VTT AVCC 3VSB
VBAT
3VCC 3VCC
W83627DHG
Pin Layout for W83627DHG UBC version
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3VSB
GP37 KDAT/GP26 KCLK/GP27 3VSB KBRST GA20M SI/AUXFANIN1 RIA#/GP60 DCDA#/GP61 VSS SOUTA/GP62(PENKBC) SINA/GP63 DTRA#/GP64(PENROM) RTSA#/GP65(HEFRAS) DSRA#/GP66 CTSA#/GP67 3VCC STB# AFD# ERR# INIT# SLIN# PD0 PD1 PD2 PD3
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
AUXTIN VREF CPUVCORE VIN0 VIN1 VIN2 VIN3 AVCC RSTOUT0# RSTOUT1# GP30 GP31 GP32/RSTOUT2#/SCL GP33/RSTOUT3#/SDA GP34/RSTOUT4# GP35 PME# GP40/RIB# GP41/DCDB# GP42/SOUTB/IRTX(FAN_SET2) GP43/SINB/IRRX GP44/DTRB# GP45/RTSB# GP46/DSRB# GP47/CTSB# GP50/WDTO#(EN_GTL) CASEOPEN# RSMRST#/GP51 VBAT SUSB#/GP52 PSON#/GP53 PWROK/GP54 GP55/SUSLED GP36 PSIN#/GP56 PSOUT#/GP57 MDAT/GP24 MCLK/GP25
W83627DHG
Publication Release Date: Aug, 22, 2007 Version 1.4
CPUTIN SYSTIN CPUDPECISB Vtt PECI NC NC AUXFANIN0 CPUFANIN0 SYSFANIN SST CPUFANOUT0 SYSFANOUT (FAN_SET)PLED BEEP/SO GP21/CPUFANIN1 GP20/CPUFANOUT1 VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
DRVDEN0 GP23/SCK INDEX# MOA# SMI#/OVT# DSA# AUXFANOUT DIR# STEP# WD# WE# 3VCC TRAK0# WP# RDATA# HEAD# DSKCHG# IOCLK GP22/SCE VSS PCICLK LDRQ# SERIRQ LAD3 LAD2 LAD1 LAD0 3VCC LFRAME# LRESET# SLCT PE BUSY ACK# PD7 PD6 PD5 PD4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
3VCC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
Pin Layout for W83627DHG UBE and UBF version
VTT AVCC 3VSB
VBAT
3VCC
W83627DHG
3VCC
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3VSB
GP37/SUSC# KDAT/GP26 KCLK/GP27 3VSB KBRST GA20M SI/AUXFANIN1 RIA#/GP60 DCDA#/GP61 VSS SOUTA/GP62(PENKBC) SINA/GP63 DTRA#/GP64(PENROM) RTSA#/GP65(HEFRAS) DSRA#/GP66 CTSA#/GP67 3VCC STB# AFD# ERR# INIT# SLIN# PD0 PD1 PD2 PD3
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
AUXTIN VREF CPUVCORE VIN0 VIN1 VIN2 VIN3 AVCC RSTOUT0# RSTOUT1# GP30/PWROK2 GP31/VSBGATE# GP32/RSTOUT2#/SCL GP33/RSTOUT3#/SDA GP34/RSTOUT4# GP35/ATXPGD PME# GP40/RIB# GP41/DCDB# GP42/SOUTB/IRTX(FAN_SET2) GP43/SINB/IRRX GP44/DTRB# GP45/RTSB# GP46/DSRB# GP47/CTSB# GP50/WDTO#(EN_GTL) CASEOPEN# RSMRST#/GP51 VBAT SUSB#/GP52 PSON#/GP53 PWROK/GP54 GP55/SUSLED(EN_ACPI) GP36/FTPRST# PSIN#/GP56 PSOUT#/GP57 MDAT/GP24 MCLK/GP25
W83627DHG
Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
5. PIN DESCRIPTION
- Analog output pin - Analog input pin - CMOS-level input pin with internal pull-down resistor - CMOS-level, Schmitt-trigger input pin - CMOS-level, Schmitt-trigger input pin with internal pull-up resistor - TTL-level input pin - TTL-level input pin with internal pull-down resistor - TTL-level, Schmitt-trigger input pin - 3.3V, TTL-level input pin - 3.3V TTL level Schmitt-trigger input pin - TTL-level input pin with internal pull-up resistor - bi-directional pin with 8-mA source-sink capability - TTL-level, bi-directional pin with 8-mA source-sink capability - bi-directional pin with 12-mA source-sink capability - TTL-level, bi-directional pin with 12-mA source-sink capability - Schmitt-trigger, bi-directional pin with 12-mA source-sink capability - 3.3V, TTL-level, bi-directional pin with 12-mA source-sink capability - TTL-level, bi-directional pin. Open-drain output with 8-mA sink capability - Bi-directional pin. Open-drain output with 12-mA sink capability - TTL-level bi-directional pin. Open-drain output with 12-mA sink capability - CMOS-level, bi-directional, Schmitt-trigger pin. Open-drain output with 12-mA sink capability - TTL-level, bi-directional, Schmitt-trigger pin. Open-drain output with 12-mA sink capability - 3.3V, TTL-level, bi-directional pin. Open-drain output with 12-mA sink capability - TTL-level, bi-directional pin. Open-drain output with 16-mA sink capability - Schmitt-trigger, bi-directional pin. Open-drain output with 16-mA sink capability - CMOS-level, Schmitt-trigger, bi-directional pin. Open-drain output with 16-mA sink capability - TTL-level, bi-directional pin. Open-drain output with 24-mA sink capability - 3.3V output pin with 12-mA source-sink capability - 3.3V, TTL-level output pin with 12-mA source-sink capability - TTL-level output pin with 8-mA source-sink capability - TTL-level output pin with 12-mA source-sink capability - TTL-level output pin with 24-mA source-sink capability - Open-drain output pin with 8-mA sink capability - Open-drain output pin with 12-mA sink capability - Open-drain output pin with 24-mA sink capability - Bi-direction pin with source capability of 6 mA and sink capability of 1 mA
Note: Please refer to Section 21.2 DC CHARACTERISTICS for details. AOUT AIN INcd INcs INcsu INt INtd INts INtp3 INtsp3 INtu I/O8 I/O8t I/O12 I/O12t I/O12ts I/O12tp3 I/OD8t I/OD12 I/OD12t I/OD12cs I/OD12ts I/OD12tp3 I/OD16t I/OD16ts I/OD16cs I/OD24t O12p3 O12tp3 O8 O12 O24 OD8 OD12 OD24 I/OV3
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
5.1 LPC Interface
PIN I/O DESCRIPTION
SYMBOL
IOCLK PME# PCICLK LDRQ# SERIRQ LAD[3:0] LFRAME# LRESET#
18 86 21 22 23 24-27 29 30
INtp3 OD12p3 INtsp3 O12p3 I/OD12tp3 I/O12tp3 INtsp3 INtsp3
System clock input, either 24MHz or 48MHz. The actual frequency must be specified in the register. The default value is 48MHz. Generated PME event. PCI-clock 33-MHz input. Encoded DMA Request signal. Serialized IRQ input / output. These signal lines communicate address, control, and data information over the LPC bus between a host and a peripheral. Indicates the start of a new cycle or the termination of a broken cycle. Reset signal. It can be connected to the PCIRST# signal on the host.
5.2
FDC Interface
PIN I/O DESCRIPTION
SYMBOL
DRVDEN0 INDEX#
1 3
OD24 INcs
Drive Density Select bit 0. This Schmitt-trigger input from the disk drive is active-low when the head is positioned over the beginning of a track marked by an index hole. This input pin needs to connect a pulled-up 1-K resistor to 5V for Floppy Drive compatibility. Motor A On. When set to 0, this pin activates disk drive A. This is an open-drain output. Drive Select A. When set to 0, this pin activates disk drive A. This is an open-drain output. Direction of the head step motor. An open-drain output. Logic 1 = outward motion Logic 0 = inward motion Step output pulses. This active-low open-drain output produces a pulse to move the head to another track. Write data. This logic-low open-drain writes pre-compensation serial data to the selected FDD. An open-drain output. Write enable. An open-drain output. Track 0. This Schmitt-trigger input from the disk drive is active-low when the head is positioned over the outermost track. This input pin needs to connect a pulled-up 1-K resistor to 5V for Floppy Drive compatibility.
MOA# DSA#
4 6
OD24 OD24 OD24 OD24 OD24 OD24 INcs
DIR#
8
STEP# WD# WE# TRAK0#
9 10 11 13
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
FDC Interface, continued
SYMBOL
PIN
I/O
DESCRIPTION
WP# RDATA#
14 15
INcs INcs
Write protected. This active-low Schmitt input from the disk drive indicates that the diskette is write-protected. This input pin needs to connect a pulled-up 1-K resistor to 5V for Floppy Drive compatibility. The read-data input signal from the FDD. This input pin needs to connect a pulled-up 1-K resistor to 5V for Floppy Drive compatibility. Head selection. This open-rain output determines which disk drive head is active. Logic 1 = side 0 Logic 0 = side 1 Diskette change. This signal is active-low at power-on and whenever the diskette is removed. This input pin needs to connect a pulled-up 1-K resistor to 5V for Floppy Drive compatibility.
HEAD#
16
OD24
DSKCHG#
17
INcs
5.3
Multi-Mode Parallel Port
PIN I/O DESCRIPTION
SYMBOL
SLCT
31
INts
PRINTER MODE: An active-high input on this pin indicates that the printer is selected. See the description of the parallel port for the definition of this pin in ECP and EPP modes. PRINTER MODE: An active-high input on this pin indicates that the printer has detected the end of the paper. See the description of the parallel port for the definitions of this pin in ECP and EPP modes. PRINTER MODE: An active-high input indicates that the printer is not ready to receive data. See the description of the parallel port for the definitions of this pin in ECP and EPP modes. PRINTER MODE: ACK# An active-low input on this pin indicates that the printer has received data and is ready to accept more data. See the descriptions of the parallel port for the definition of this pin in ECP and EPP modes. PRINTER MODE: ERR# An active-low input on this pin indicates that the printer has encountered an error condition. See the description of the parallel port for the definitions of this pin in ECP and EPP modes. PRINTER MODE: SLIN# Output line for detection of printer selection. See the description of the parallel port for the definitions of this pin in ECP and EPP modes.
PE
32
INts
BUSY
33
INts
ACK#
34
INts
ERR#
45
INts
SLIN#
43
OD12
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
Multi-Mode Parallel Port, continued.
SYMBOL
PIN
I/O
DESCRIPTION
INIT#
44
OD12
PRINTER MODE: INIT# Output line for the printer initialization. See the description of the parallel port for the definitions of this pin in ECP and EPP modes. PRINTER MODE: AFD# An active-low output from this pin causes the printer to auto feed a line after a line is printed. See the description of the parallel port for the definitions of this pin in ECP and EPP modes. PRINTER MODE: STB# An active-low output is used to latch the parallel data into the printer. See the description of the parallel port for the definitions of this pin in ECP and EPP modes. PRINTER MODE: PD0 Parallel port data bus bit 0. See the description of the parallel port for the definitions of this pin in ECP and EPP modes. PRINTER MODE: PD1 Parallel port data bus bit 1. See the description of the parallel port for the definitions of this pin in ECP and EPP modes. PRINTER MODE: PD2 Parallel port data bus bit 2. See the description of the parallel port for the definitions of this pin in ECP and EPP modes. PRINTER MODE: PD3 Parallel port data bus bit 3. See the description of the parallel port for the definitions of this pin in ECP and EPP modes. PRINTER MODE: PD4 Parallel port data bus bit 4. See the description of the parallel port for the definition of this pin in ECP and EPP modes. PRINTER MODE: PD5 Parallel port data bus bit 5. See the description of the parallel port for the definitions of this pin in ECP and EPP modes. PRINTER MODE: PD6 Parallel port data bus bit 6. See the description of the parallel port for the definitions of this pin in ECP and EPP modes. PRINTER MODE: PD7 Parallel port data bus bit 7. See the description of the parallel port for the definitions of this pin in ECP and EPP modes.
AFD#
46
OD12
STB#
47
OD12
PD0
42
I/O12ts
PD1
41
I/O12ts
PD2
40
I/O12ts
PD3
39
I/O12ts
PD4
38
I/O12ts
PD5
37
I/O12ts
PD6
36
I/O12ts
PD7
35
I/O12ts
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
5.4 Serial Port & Infrared Port Interface
PIN I/O DESCRIPTION
SYMBOL
RIA# GP60 DCDA# GP61 SOUTA
57
INt I/OD12t
56
INt I/OD12t O8
PENKBC
54
INt
GP62 SINA GP63 DTRA# 53
I/O8 INt I/OD12t O8
PENROM
52
INt
GP64 RTSA#
I/O8 O8
HEFRAS
51
INt
GP65 DSRA# GP66 50
I/O8 INt I/OD12t
Ring Indicator. An active-low signal indicates that a ring signal is being received from the modem or the data set. General-purpose I/O port 6 bit 0. Data Carrier Detection. An active-low signal indicates the modem or data set has detected a data carrier. General-purpose I/O port 6 bit 1. UART A Serial Output. This pin is used to transmit serial data out to the communication link. During power on reset, this pin is pulled down internally and is defined as PENKBC, and the power-on values are shown at CR24 bit 2. The PCB layout should reserve space for a 1-k resistor to pull down this pin to ensure the disabling of KBC, and a 1-k resistor is recommended to pull the pin up If wish to enable KBC. General-purpose I/O port 6 bit 2. Serial Input. This pin is used to receive serial data through the communication link. General-purpose I/O port 6 bit 3. UART A Data Terminal Ready. An active-low signal informs the modem or data set that the controller is ready to communicate. During power-on reset, this pin is pulled down internally and is defined as PENROM disabled, and the power-on values are shown at CR24 bit 1 (ENROM). The PCB layout should reserve space for a 1-k resistor to pull down this pin to ensure the disabling of SPI interface, and a 1-k resistor is recommended to pull the pin up if wish to enable ROM. General-purpose I/O port 6 bit 4. UART A Request To Send. An active-low signal informs the modem or data set that the controller is ready to send data. During power-on reset, this pin is pulled down internally and is defined as HEFRAS, which provides the power-on value for CR26 bit 6 (HEFRAS). The PCB layout should reserve space for a 1-k resistor to pull down this pin so as to ensure the selection of I/O port's configuration address to 2EH, and a 1-k resistor is recommended to pull it up if 4EH is selected as I/O ports configuration address. General-purpose I/O port 6 bit 5. Data Set Ready. An active-low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. General-purpose I/O port 6 bit 6.
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
Serial Port & Infrared Port Interface , continued.
SYMBOL
PIN
I/O
DESCRIPTION
CTSA# GP67 RIB# GP40* DCDB# GP41*** FAN_SET2
49
INt I/OD12t
85
INt I/OD12t
84
INt I/OD12t INt
SOUTB IRTX GP42*
83
O12
I/O12t
SINB IRRX GP43*** DTRB# GP44* RTSB# GP45*** DSRB# GP46* CTSB# GP47*** 78 79 80 82
INt I/OD12t
81
O12 I/OD12t O12 I/OD12t INt I/OD12t INt I/OD12t
Clear To Send. This is the modem-control input. The function of these pins can be tested by reading bit 4 of the handshake status register. General-purpose I/O port 6 bit 7. Ring Indicator. An active-low signal indicates that a ring signal is being received from the modem or the data set. General-purpose I/O port 4 bit 0. Data Carrier Detection. An active-low signal indicates the modem or data set has detected a data carrier. General-purpose I/O port 4 bit 1. Determines the initial FAN speed. Power-on configuration for 2 fan speeds, 50% or 100%. When VCC is on, this pin needs a pulled-up or a pulled-down resistor to decide whether the fan speed is 50% or 100%. Only CPUFANOUT1 is supported. UART B Serial Output. This pin is used to transmit serial data out to the communication link. IR Transmitter output. General-purpose I/O port 4 bit 2. Note: This pin changes to input state during internal PWROK from low to high, then goes back to the previous setting state. (Please see the AP Note 1 of W83627DHG) Serial Input. This pin is used to receive serial data through the communication link. IR Receiver input. General-purpose I/O port 4 bit 3. UART B Data Terminal Ready. An active-low signal informs the modem or data set that the controller is ready to communicate. General-purpose I/O port 4 bit 4. UART B Request To Send. An active-low signal informs the modem or data set that the controller is ready to send data. General-purpose I/O port 4 bit 5. Data Set Ready. An active-low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. General-purpose I/O port 4 bit 6. Clear To Send. This is the modem-control input. The function of these pins can be tested by reading bit 4 of the handshake status register. General-purpose I/O port 4 bit 7.
Note: Regarding the * sign, please see 5.11.8 GPIO-4 for detailed WDTO# / SUSLED multi-function information.
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
5.5 KBC Interface
PIN I/O DESCRIPTION
SYMBOL
GA20M KBRST KCLK GP27 KDAT GP26 MCLK GP25 MDAT GP24
59 60 62 63 65 66
O12 O12 I/OD16ts I/OD16t I/OD16ts I/OD16t I/OD16ts I/OD16t I/OD16ts I/OD16t
Gate A20 output. This pin is high after system reset. (KBC P21) Keyboard reset. This pin is high after system reset. (KBC P20) Keyboard Clock. General-purpose I/O port 2 bit 7. Keyboard Data. General-purpose I/O port 2 bit 6. PS2 Mouse Clock. General-purpose I/O port 2 bit 5. PS2 Mouse Data. General-purpose I/O port 2 bit 4.
5.6
Serial Peripheral Interface
The SPI employs a master-slave model and typically has three signal lines: serial data input line (SI), serial data output line (SO), and serial clock line (SCK). Different slaves are addressed on the bus by chip select signals from the master. The data bits are first shifted in/out the most significant bit (MSB). The data are often shifted simultaneously out from the output pin and into the input pin. Among the parameters, only the communication lines and the clock edge are defined by the SPI. The others differ from device to device. SPI Operation To initiate the data transfer between the W83627DHG and a slave device, SCE# must go low. This synchronizes the slave device with the W83627DHG. Data can now be transferred between the W83627DHG and the slave device in one of two modes: the data is sampled either on the rising or the falling edge of the clock. In a slave device, a logic low is received on the SCE# line and the clock input is at the SCK pin, which synchronizes the slave with the W83627DHG. Data is then received serially at the SI pin. During a write cycle, data is shifted out to the SO pin on clocks from the W83627DHG.
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
SYMBOL
PIN
I/O
DESCRIPTION
SCE# GP22 SCK GP23 SO
19
O12 I/OD12t O12 I/OD12t O8
Serial flash ROM interface chip selection. General-purpose I/O port 2 bit 2. Clock output for serial flash. *UBC, UBE and UBF version support 33 MHz frequency, but UBE and UBF version use 16 MHz frequency as their default. General-purpose I/O port 2 bit 3. Transfer commands, addresses or data to serial flash. This pin is connected to SI of serial flash. Beep function for hardware monitor. This pin is low after system reset. Receive data from serial flash. This pin is connected to SO of serial flash. 0 to +3 V amplitude fan tachometer input.
2
118 BEEP SI AUXFANIN1 OD8 INts I/O12ts
58
5.7
Hardware Monitor Interface
SYMBOL PIN I/O DESCRIPTION
BEEP 118 SO
OD8 O8
Beep function for hardware monitor. This pin is low after system reset. Transfer commands, address or data to serial flash. This pin is connected to SI of serial flash. CASE OPEN detection. An active-low input from an external device when the case is open. This signal can be latched if pin VBAT is connected to the battery, even if the W83627DHG is turned off. Pulling up a 2-M resistor to VBAT is recommended if not in use. Analog Inputs for voltage measurement (Range: 0 to 2.048 V) Analog Inputs for voltage measurement (Range: 0 to 2.048 V) Analog Inputs for voltage measurement (Range: 0 to 2.948 V) Analog Inputs for voltage measurement (Range: 0 to 2.048 V) Analog Inputs for voltage measurement (Range: 0 to 2.048 V) Reference Voltage (2.048 V). The input of temperature sensor 3. It is used for temperature sensing. The input of temperature sensor 2. It is used for CPU temperature sensing.
CASEOPEN#
76
INt
VIN3 VIN2 VIN1 VIN0 CPUVCORE VREF AUXTIN CPUTIN
96 97 98 99 100 101 102 103
AIN AIN AIN AIN AIN AOUT AIN AIN
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
Hardware Monitor Interface, continued.
SYMBOL
PIN
I/O
DESCRIPTION
SYSTIN OVT# SMI# VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 AUXFANIN1 SI AUXFANIN0 CPUFANIN0 SYSFANIN CPUFANIN1 GP21 AUXFANOUT CPUFANOUT0 SYSFANOUT
104
AIN OD12 OD12
The input of temperature sensor 1. It is used for system temperature sensing. The output of over temperature Shutdown. This pin indicates the temperature is over the temperature limit. (Default after LRESET#) System Management Interrupt channel output.
5 121 122 123 124 125 126 127 128 58 111 112 113 119 7 115 116
I/O12
VID input detection, also with output control.
I/O12ts INts
0 to +3 V amplitude fan tachometer input. Receive data from serial flash. This pin is connected to SO of serial flash..
I/O12ts
0 to +3 V amplitude fan tachometer input.
I/O12ts I/OD12t
0 to +3 V amplitude fan tachometer input. (Default) General-purpose I/O port 2 bit 1.
DC/PWM fan output control. AOUT/ CPUFANOUT0 and AUXFANOUT are default PWM mode, OD12/ O12 CPUFANOUT1 and SYSFANOUT are default DC mode.
CPUFANOUT1 GP20 FAN_SET PLED
120
DC/PWM fan output control. (Default) AOUT/ O12/ OD12 CPUFANOUT0 and AUXFANOUT are default PWM mode, CPUFANOUT1 and SYSFANOUT are default DC mode. I/OD12t INtd O12 General-purpose I/O port 2 bit 0.
Determines the initial FAN speed. Power on configuration for 2 fan speeds, 50% or 100%. During power-on reset, this pin is pulled down internally and the fan speed is 50%. Only CPUFANOUT0 is supported. Power LED output. Drive high 3.3 V after strapping.
117
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
5.8 PECI Interface
SYMBOL PIN I/O DESCRIPTION INTEL(R) CPU PECI interface. Connect to CPU. INTEL(R) CPU Vtt Power. This pin is connected to GND if the PECI function is not in use. INTEL(R) CPU PECI interface. Connect to ICH8.
PECI Vtt
PECISB
108 107 106
I/OV3 Power I/OBV3
5.9
SST Interface
SYMBOL PIN I/O DESCRIPTION Simple Serial Transport (SST) Interface.
SST
114
I/OV4
5.10 Advanced Configuration and Power Interface
The Advanced Configuration and Power Interface (ACPI) is an interface that allows OS-directed Power Management (OSPM). The ACPI replaces the APM (Advanced Power Management), MPS (Multiprocessor Specification), and PnP BIOS Specification. In addition to power management, the ACPI supports the functions of thermal management, state management, and speed control, as well as the global system states and different device power states. Two of the primary states that the W83627DHG supports are the S0 (working) and S3 (suspend to RAM) states. S0 is a full-power state, in which the computer is actively used. S3 is a sleeping state, in which the processor is powered down, but the memory, where the last procedural state is stored, is still active. By employing the ACPI, the system conserves more energy through transiting unused devices into lower power states, including placing the entire system in a low-power state when possible.
SYMBOL PIN I/O DESCRIPTION
PSIN# GP56 PSOUT# GP57
RSMRST#
68
INtu I/OD12t
Panel Switch Input. This pin is active-low with an internal
pulled-up resistor.
General-purpose I/O port 5 bit 6. Panel Switch Output. This signal is used to wake-up the system from S3/S5 state. General-purpose I/O port 5 bit 7.
Resume reset signal output. General-purpose I/O port 5 bit 1. System S3 state input. General-purpose I/O port 5 bit 2. Power supply on-off output. General-purpose I/O port 5 bit 3. This pin generates the PWROK signal while 3VCC comes in. General-purpose I/O port 5 bit 4.
67
OD12 I/OD12t
GP51
SUSB# GP52 PSON# GP53 PWROK GP54
75 73 72 71
OD12 I/OD12t INt I/OD12t OD12 I/OD12t OD12 I/OD12t
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
Continued
SYMBOL
PIN
I/O
DESCRIPTION
RSTOUT0# RSTOUT1# RSTOUT2# GP32 SCL RSTOUT3# GP33 SDA RSTOUT4# GP34
94 93 90
OD12 O12 O12 I/OD12t INts O12
PCI Reset Buffer 0. PCI Reset Buffer 1. PCI Reset Buffer 2. (Default) General-purpose I/O port 3 bit 2. Serial Bus clock. PCI Reset Buffer 3. (Default) General-purpose I/O port 3 bit 3. Serial bus bi-directional Data. PCI Reset Buffer 4. (Default) General-purpose I/O port 3 bit 4.
89
I/OD12t I/OD12ts O12 I/OD12t
88
5.11 General Purpose I/O Port
5.11.1 SMBus Interface
SYMBOL PIN I/O DESCRIPTION
RSTOUT2# GP32 SCL RSTOUT3# GP33 SDA 89 90
O12 I/OD12t INts O12 I/OD12t I/OD12ts
PCI Reset Buffer 2. (Default) General-purpose I/O port 3 bit 2. Serial Bus clock. PCI Reset Buffer 3. (Default) General-purpose I/O port 3 bit 3. Serial bus bi-directional Data.
5.11.2 GPIO Power Source
SYMBOL POWER SOURCE
GPIO port 2 (Bit0-3) GPIO port 2 (Bit4-7) GPIO port 3 GPIO port 4 GPIO port 5 GPIO port 6
3VCC 3VSB 3VSB 3VSB 3VSB 3VCC
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
5.11.3 GPIO-2 Interface
SYMBOL PIN I/O DESCRIPTION
GP20 CPUFANOUT1 GP21 CPUFANIN1 GP22 SCE# GP23 SCK GP24 MDAT GP25 MCLK GP26 KDAT GP27 KCLK 2 120
I/OD12t AOUT/ OD12/ O12 I/OD12t I/O12ts I/OD12t O12 I/OD12t O12 I/OD16t I/OD16ts I/OD16t I/OD16ts I/OD16t I/OD16ts I/OD16t I/OD16ts
General-purpose I/O port 2 bit 0. DC/PWM fan output control. (Default) CPUFANOUT0 and AUXFANOUT are default PWM mode, CPUFANOUT1 and SYSFANOUT are default DC mode. General-purpose I/O port 2 bit 1. 0 to +3 V amplitude fan tachometer input. (Default) General-purpose I/O port 2 bit 2. Serial flash ROM interface chip selection. General-purpose I/O port 2 bit 3. Clock output for serial flash. *UBC, UBE and UBF version support 33 MHz frequency, but UBE and UBF version use 16 MHz frequency as their default. General-purpose I/O port 2 bit 4. PS2 Mouse Data. General-purpose I/O port 2 bit 5. PS2 Mouse Clock. General-purpose I/O port 2 bit 6. Keyboard Data. General-purpose I/O port 2 bit 7. Keyboard Clock.
119 19
66 65 63 62
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
5.11.4 GPIO-3 Interface
SYMBOL PIN I/O DESCRIPTION
RSTOUT0# RSTOUT1# GP30 PWROK2 GP31 VSBGATE# GP32 RSTOUT2# SCL GP33 RSTOUT3# SDA GP34 RSTOUT4# GP35 ATXPGD GP36 FTPRST# GP37 SUSC#
94 93 92
OD12 O12 I/OD12t OD12 I/OD12t
91
O12 I/OD12t O12 INts I/OD12t O12 I/OD12ts I/OD12t O12 I/OD12t INt I/OD12t
90
89 88
87
69
INt I/OD12t
64
INt
PCI Reset Buffer 0. PCI Reset Buffer 1. General-purpose I/O port 3 bit 0. This pin generates the PWROK2 signal while 3VCC comes in. (This pin function is both for UBE and UBF version only) General-purpose I/O port 3 bit 1. Switch 3VSB power to memory when in S3 state. The default is disabled while the particular ACPI functions are enabled. The control bit is at Logical Device A, CR[E4h] bit 4.(This pin function is both for UBE and UBF version only) General-purpose I/O port 3 bit 2. PCI Reset Buffer 2. (Default) Serial Bus clock. General-purpose I/O port 3 bit 3. PCI Reset Buffer 3. (Default) Serial bus bi-directional Data. General-purpose I/O port 3 bit 4. PCI Reset Buffer 4. (Default) General-purpose I/O port 3 bit 5. ATX power good input signal. It is connected to the PWROK signal from the power supply for PWROK/PWROK2 generation. The default is enabled.(This pin function is both for UBE and UBF version only) General-purpose I/O port 3 bit 6. Connect to the reset button. This pin has internal de-bounce circuit whose de-bounce time is at least 32 mS. (This pin function is both for UBE and UBF version only) General-purpose I/O port 3 bit 7. SLP_S5# input. (This pin function is both for UBE and UBF version only)
5.11.5 GPIO-4 Interface See 5.4 Serial Port & Infrared Port Interface
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
5.11.6 GPIO-5 Interface
SYMBOL PIN I/O DESCRIPTION
GP50
I/O12t
General-purpose I/O port 5 bit 0. (Default after strapping) During VSB power reset (RSMRST), this pin is pulled high internally and is defined as VID transition voltage level (GTL or TTL), and the value is shown at CR2C bit 3. The PCB layout should reserve space for a 1-k resistor to pull down this pin if TTL is the selected VID level. Watchdog Timer output signal. General-purpose I/O port 5 bit 1. Resume reset signal output. General-purpose I/O port 5 bit 2. System S3 state input. General-purpose I/O port 5 bit 3. Power supply on-off output. General-purpose I/O port 5 bit 4. This pin generates the PWROK signal while 3VCC comes in. General-purpose I/O port 5 bit 5. (Default) During VSB power reset (RSMRST), this pin is pulled down internally and is defined as EN_ACPI (enabling particular ACPI functions), which provides the value for CR2C bit 4 (EN_ACPI). The PCB layout should reserve space for a 1-k resistor to pull down this pin to ensure successful disabling of particular ACPI functions, and a 1-k resistor is recommended to pull the pin up if wish to enable particular ACPI functions. (This pin function is both for UBE and UBF version only) Suspended LED output. General-purpose I/O port 5 bit 6. Panel Switch Input. This pin is active-low with an internal pulled-up
resistor.
EN_GTL
77
INcu
WDTO# GP51 RSMRST# GP52 SUSB# GP53 PSON# GP54 PWROK GP55 75 73 72 71
O12 I/OD12t OD12 I/OD12t INt I/OD12t OD12 I/OD12t OD12 I/O12t
EN_ACPI
70
INcd
SUSLED GP56 PSIN# GP57 PSOUT# 67 68
O12 I/OD12t INtu I/OD12t OD12
General-purpose I/O port 5 bit 7. Panel Switch Output. This signal is used to wake-up the system from S3/S5 state.
5.11.7 GPIO-6 Interface See 5.4 Serial Port & Infrared Port Interface
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
5.11.8 GPIO-4 with WDTO# / SUSLED Multi-function
SYMBOL PIN I/O DESCRIPTION
GPxx* WDTO# GPxx*** SUSLED
-----
I/OD12t OD12 I/OD12t OD12
This GPxx* can serve as GPIO or the Watchdog Timer output signals. This GPxx*** can serve as GPIO or Suspend-LED output signals.
5.12 Particular ACPI Function pins - both for UBE and UBF Version Only
SYMBOL PIN I/O DESCRIPTION
SUSC# GP37
64
INt I/OD12t
SLP_S5# input. (This pin function is both for UBE and UBF version only) General-purpose I/O port 3 bit 7 During VSB power reset (RSMRST), this pin is pulled down internally and is defined as EN_ACPI (enabling particular ACPI functions), which provides the value for CR2C bit 4 (EN_ACPI). The PCB layout should reserve space for a 1-k resistor to pull down this pin to ensure successful disabling of particular ACPI functions, and a 1-k resistor is recommended to pull the pin up if wish to enable particular ACPI functions. (This pin function is both for UBE and UBF version only) General-purpose I/O port 5 bit 5. Suspended LED output. Switch 3VSB power to memory when in S3 state. The default is disabled while the particular ACPI functions are enabled. The control bit is at Logical Device A, CR[E4h] bit 4. (This pin function is both for UBE and UBF version only) General-purpose I/O port 3 bit 1. This pin generates the PWROK2 signal while 3VCC comes in. (This pin function is both for UBE and UBF version only) General-purpose I/O port 3 bit 0. ATX power good input signal. It is connected to the PWROK signal from the power supply for PWROK/PWROK2 generation. The default is enabled. (This pin function is both for UBE and UBF version only) General-purpose I/O port 3 bit 5. Connect to the reset button. This pin has internal de-bounce circuit whose de-bounce time is at least 32 mS. (This pin function is both for UBE and UBF version only) General-purpose I/O port 3 bit 6.
EN_ACPI 70
INcd
GP55 SUSLED VSBGATE# GP31 PWROK2 GP30 ATXPGD GP35 FTPRST# GP36 69 92
I/O12t O12 O12 I/OD12t OD12 I/OD12t INt I/OD12 INt I/OD12
91
87
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
5.13 POWER PINS
SYMBOL PIN DESCRIPTION
3VSB VBAT 3VCC AVCC CPUD(AGND) VSS Vtt
61 74 12,28,48 95 105 20,55 107
+3.3 V stand-by power supply for the digital circuits. +3 V on-board battery for the digital circuits. +3.3 V power supply for driving 3 V on host interface. Analog +3.3 V power input. Internally supply power to all analog circuits. Analog ground. The ground reference for all analog input. Internally connected to all analog circuits. Ground. INTEL(R) CPU Vtt power.
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
6. CONFIGURATION REGISTER ACCESS PROTOCOL
The W83627DHG uses Super I/O protocol to access configuration registers to set up different types of configurations. The W83627DHG has totally twelve Logical Devices (from Logical Device 0 to Logical Device C with the exception of Logical Device 4 for backward compatibility) corresponding to twelve individual functions: FDC (Logical Device 0), Parallel Port (Logical Device 1), UARTA (Logical Device 2), UARTB (Logical Device 3), Keyboard Controller (Logical Device 5), SPI (Serial Peripheral Interface, Logical Device 6), GPIO6 (Logical Device 7), WDTO# & PLED (Logical Device 8), GPIO2, 3, 4, 5 (Logical Device 9), ACPI (Logical Device A), Hardware Monitor (Logical Device B), and PECI & SST (Logical Device C). Each Logical Device has its own configuration registers (above CR30). The host can access those registers by writing an appropriate Logical Device Number into the Logical Device select register at CR7. Please note that GPIO1 is not defined in the W83627DHG.
Logical Device No. Logical Device Control Logical Device Configuration
#1 #2 #C
#0
One Per Logical Device
Devices of I/O Base Address
LOGICAL DEVICE NUMBER FUNCTION I/O BASE ADDRESS
0 1 2 3 4 5 6 7 8 9 A B C
FDC Parallel Port UART A UART B Reserved Keyboard Controller Serial Peripheral Interface GPIO 6 WDTO# & PLED GPIO 2, 3, 4, 5 ACPI Hardware Monitor PECI & SST
100h ~ FF8h 100h ~ FF8h 100h ~ FF8h 100h ~ FF8h 100h ~ FFFh 100h ~ FF8h 100h ~ FFFh Reserved Reserved Reserved 100h ~ FFEh Reserved
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
6.1 Configuration Sequence
Power-on Reset
Any other I/O transition cycle
Wait for key string
I/O Write to 2Eh
N
Is the data "87h"? Y Check Pass key
I/O Write to 2Eh
Any other I/O transition cycle
N
Is the data "87h"? Y Extended Function Mode
To program the W83627DHG configuration registers, the following configuration procedures must be followed in sequence: (1). Enter the Extended Function Mode. (2). Configure the configuration registers. (3). Exit the Extended Function Mode.
6.1.1 Enter the Extended Function Mode To place the chip into the Extended Function Mode, two successive writes of 0x87 must be applied to Extended Function Enable Registers (EFERs, i.e. 2Eh or 4Eh). 6.1.2 Configure the Configuration Registers The chip selects the Logical Device and activates the desired Logical Devices through Extended Function Index Register (EFIR) and Extended Function Data Register (EFDR). The EFIR is located at the same address as the EFER, and the EFDR is located at address (EFIR+1). First, write the Logical Device Number (i.e. 0x07) to the EFIR and then write the number of the desired Logical Device to the EFDR. If accessing the Chip (Global) Control Registers, this step is not required. Secondly, write the address of the desired configuration register within the Logical Device to the EFIR and then write (or read) the desired configuration register through the EFDR.
Publication Release Date: Aug, 22, 2007 Version 1.4
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W83627DHG
6.1.3 Exit the Extended Function Mode To exit the Extended Function Mode, writing 0xAA to the EFER is required. Once the chip exits the Extended Function Mode, it is in the normal running mode and is ready to enter the configuration mode. 6.1.4 Software Programming Example The following example is written in Intel 8086 assembly language. It assumes that the EFER is located at 2Eh, so the EFIR is located at 2Eh and the EFDR is located at 2Fh. If the HEFRAS (CR26 bit 6) is set, 2Eh can be directly replaced by 4Eh and 2Fh replaced by 4Fh.
;----------------------------------------------------; Enter the Extended Function Mode ;----------------------------------------------------MOV DX, 2EH MOV AL, 87H OUT DX, AL OUT DX, AL ;----------------------------------------------------------------------------; Configure Logical Device 1, Configuration Register CRF0 ;----------------------------------------------------------------------------MOV DX, 2EH MOV AL, 07H OUT DX, AL ; point to Logical Device Number Reg. MOV DX, 2FH MOV AL, 01H OUT DX, AL ; select Logical Device 1 ; MOV DX, 2EH MOV AL, F0H OUT DX, AL ; select CRF0 MOV DX, 2FH MOV AL, 3CH OUT DX, AL ; update CRF0 with value 3CH ;---------------------------------------------------------------------------; Exit the Extended Function Mode ;---------------------------------------------------------------------------MOV DX, 2EH MOV AL, AAH OUT DX, AL
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
Chip (Global) Control Registers
INDEX R/W DEFAULT VALUE DESCRIPTION
02h 07h 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh S: Strapping; x: chip version.
Write Only R/W Read Only Read Only R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 00h A0h 2xh FFh 00h 0100_0ss0b 00h 0s000000b Reserved 50h 00h 00h Reserved E2h 21h 00h 00h
Software Reset Logical Device Chip ID, MSB Chip ID, LSB Device Power Down Immediate Power Down Global Option Interface Tri-state Enable Global Option Global Option Multi-function Pin Selection SPI Configuration Multi-function Pin Selection Multi-function Pin Selection Reserved Reserved
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
7. HARDWARE MONITOR 7.1 General Description
The W83627DHG monitors several critical parameters in PC hardware, including power supply voltages, fan speeds, and temperatures, all of which are very important for a high-end computer system to work stably and properly. The W83627DHG can simultaneously monitor all of the following inputs: * Nine analog voltage inputs (four intrinsic monitor VBAT, 3VSB, 3VCC and AVCC power; five externally monitored power) * Five fan tachometer inputs * Three remote temperatures, by thermistor or from the CPU thermal-diode output(voltage or Current Mode) * One case-open detection signal. These inputs are converted to digital values using a built-in, eight-bit analog-to-digital converter (ADC). In response to these inputs, the W83627DHG can generate the following outputs: * Four PWM (pulse width modulation) or DC fan outputs for the fan speed control * Beep tone output for warnings * SMI# * OVT# signals for system protection events The W83627DHG provides hardware access to all monitored parameters through the LPC or I2C interface and software access through application software, such as Winbond's Hardware DoctorTM, or BIOS. In addition, the W83627DHG can generate pop-up warnings or beep tones when a parameter goes outside of a user-specified range. The rest of this section introduces the various features of the W83627DHG hardware-monitor capability. These features are divided into the following sections: * * * * * * * Access Interfaces Analog Inputs Fan Speed Measurement and Control Smart Fan Control SMI# interrupt mode OVT# interrupt mode Registers and Value RAM
7.2
Access Interfaces
The W83627DHG provides two interfaces, LPC and I2C, for the microprocessor to read or write the internal registers of the hardware monitor.
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
7.2.1 LPC Interface This interface uses the LPC bus to access the index and data ports. These two ports are located at the 16-bit port specified in CR60 and CR61, plus 5h and 6h, respectively. If the 16-bit port value is 290h, so the default index and data port addresses are 295h and 296h, respectively. The structure of the internal registers is shown in the following figure.
Smart Fan Configuration Registers 00h-1Fh Monitor Value Registers 20h~3Fh
BANK 0 FANOUT Critical Temperature 6Bh~6Eh
Configuration Register 40h Interrupt Status Registers 41h, 42h SMI# Mask Registers 43h, 44h, 46h Fan Divisor Register I LPC Bus 47h Serial Bus Address 48h Port 5h FANOUTs Source Select Register Index Register 49h, 4Ah BANK 4 Fan Divisor Register II 4Bh SMI#/OVT# Control Register 4Ch BANK 4 Temperature Offset Registers 54h~56h Beep Control Registers 53h BANK 2 AUXTIN Temperature Control/Status Registers 50h~56h BANK 1 CPUTIN Temperature Control/Status Registers 50h~56h
BANK 4 Interrupt Status & SMI# Mask Registers 50h~51h
Fan IN /OUT Control Register 4Dh Bank Select for 50h~5Fh Registers. 4Eh Port 6h Data Register Winbond Vendor ID 4Fh BANK 0 BEEP Control Registers 56h~57h BANK 0 Chip ID Register 58h BANK 0 Temperature Sensor Type Configuration & Fan Divisor Registers 59h,5Dh BANK 0 Critical Temperature and Current Mode enable 5Eh BANK 0 Smart Fan Configuration Registers 60h~6Ah
BANK 4 Read Time Status Registers 59h~5Bh
BANK 5 Monitor Value Registers 50h~5Ch
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
7.2.2 I2C interface This interface uses the I2C Serial Bus to access the internal registers. The W83627DHG has a programmable serial-bus address that is controlled by index 48h.
The two timing diagrams below illustrate how to use the I2C interface to write to an internal register and how to read the value in an internal register, respectively. (a) Serial bus write to internal address register followed by the data byte
0 SCL SDA
Start By Master
7
8
0
7
8
0
1
0
1
1
0
1
R/W
Ack by 627DHG
D7
D6
D5
D4
D3
D2
D1
D0
Ack by 627DHG
Frame 1 Serial Bus Address Byte 0
Frame 2 Internal Index Register Byte
7 SCL (Continued) SDA (Continued) D7 D6 D5 D4 D3 D2 D1 D0
8
Ack Ack by by 627DHG 784R
Stop by Master
Frame 3 Data Byte
(b) Serial bus read from a register
0 SCL SDA
Start By Master
7
8
0
7
8
0
1
0
1
1
0
1
R/W
Ack by 627DHG
D7
D6
D5
D4
D3
D2
D1
D0
Ack by 627DHG
Frame 1 Serial Bus Address Byte 0
Frame 2 Internal Index Register Byte
0
7
8
0
7
8
0
Repeat start by Master
1
0
1
1
0
1
R/W
Ack by 627DHG
D7
D6
D5
D4
D3
D2
D1
D0
Ack by Master Stop by Master
Frame 3 Serial Bus Address Byte 0
Frame 4 Data Byte
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
7.3 Analog Inputs
The maximum input voltage on analog pins is 2.048 V because the 8-bit ADC has an 8-mV LSB. Usually, the voltage ports of CPU Vcore (pin 100), battery (pin 74), 3VSB (pin 61), 3VCC (pin 12), and AVCC (pin 95) can be directly connected to their respective analog pins, as illustrated in the figure below.
AVCC Power Inputs VBAT 3VSB 3VCC CPUVCORE
Pin 95 Pin 74 Pin 61 Pin 12 Pin 100
R1 V0 R2
VIN0
Pin 99
Positive Voltage Input VIN2 VIN3 Pin 97 Pin 96 8-bit ADC with 8mV LSB
R3 Negative Voltage Input V1
VIN1
Pin 98
R4 RTHM 10K@25 C, beta=3435K R 10K, 1% VREF R 15K, 1% AUXTIN CPUTIN SYSTIN CPUD+ CAP,2200p CPUD(AGND) CPUD-(AGND) Pin 105 Pin 102 Pin 103 Pin 104 Pin 101
As illustrated in the figure above, other connections may require some external circuits. The rest of this section provides more information about voltages outside the range of the 8-bit ADC, CPU Vcore voltage detection, and temperature sensing
7.3.1 Voltages Over 2.048 V or Less Than 0 V Input voltages greater than 2.048 V should be reduced by external resistors to keep the input voltages in the proper range. For example, input voltage V0 (+12 V) should be reduced before it is connected to VIN0 according to the following equation:
VIN 0 = V 0 x
R2 R1 + R2
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
R1 and R2 can be set to 56 K and 10 K, respectively, to reduce V0 from +12 V to less than 2.048 V. The W83627DHG uses the same approach. Pins 12 and 95 provide two functions. One, these pins are connected to VCC at +3.3 V to supply internal (digital / analog) power to the W83627DHG. Two, these pins monitor VCC. The W83627DHG has two internal, 34-K serial resistors that reduce the ADC-input voltage to 1.65 V.
Vin = VCC x
34 K 1.65V , where VCC is set to 3.3V 34 K + 34 K
Pin 61 is implemented likewise to monitor its +3.3 V stand-by power supply. Negative voltages are handled similarly, though the equation looks a little more complicated. For example, negative voltage V1 (-12V) can be reduced according to the following equation:
VIN1 = (V 1 - 2.048) x
R4 + 2.048, whereV 1 = -12 R3 + R 4
R3 and R4 can be set to 232 K and 10 K, respectively, to reduce negative input voltage V1 from -12 V to less than 2.048 V. Both of these solutions are illustrated in the figure above.
7.3.2 Voltage Detection The data format for voltage detection is an eight-bit value, and each unit represents an interval of 8 mV. Detected Voltage = Reading * 0.008 V If the source voltage was reduced, the detected voltage value may have to be scaled up accordingly. 7.3.3 Temperature Sensing The data format for sensor SYSTIN is 8-bit, two's-complement, and the data format for sensors CPUTIN and AUXTIN is 9-bit, two's-complement. This is illustrated in the table below.
TEMPERATURE 8-BIT DIGITAL OUTPUT 8-BIT BINARY 8-BIT HEX 9-BIT DIGITAL OUTPUT 9-BIT BINARY 9-BIT HEX
+125C +25C +1C +0.5C +0C -0.5C -1C -25C -55C
0111,1101 0001,1001 0000,0001 0000,0000 1111,1111 1110,0111 1100,1001
7Dh 19h 01h 00h FFh E7h C9h
0,1111,1010 0,0011,0010 0,0000,0010 0,0000,0001 0,0000,0000 1,1111,1111 1,1111,1110 1,1100,1110 1,1001,0010
0FAh 032h 002h 001h 000h 1FFh 1FFh 1CEh 192h
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
Eight-bit temperature data is read from Index[27h]. For nine-bit temperature data, the 8 MSB are read from Bank1 / Bank2 Index[50h], and the LSB is read from Bank1 / Bank2 Index[51h], bit 7. There are two sources of temperature data: external thermistors or thermal diodes. 7.3.3.1. Monitor Temperature From Thermistor External thermistors should have a value of 3435K and a resistance of 10 K at 25C. As illustrated in the schematic below, the thermistor is connected in series with a 10-K resistor and then connects to VREF (pin 101).
RTHM 10K@25 C, beta=3435K
R 10K, 1% VREF AUXTIN CPUTIN SYSTIN Pin 101 Pin 102 Pin 103 Pin 104
W83627DHG
7.3.3.2. Monitor Temperature from Thermal Diode (Voltage Mode) The thermal diode D- pin is connected to CPUD-(pin 105), and the D+ pin is connected to the temperature sensor pin in the W83627DHG. A 15-K resistor is connected to VREF to supply the bias current for the diode, and the 2200-pF, bypass capacitor is added to filter high-frequency noise.
VREF
R=15K,1%
W83627DHG
D+ Therminal Diode C=2200pF D-
(SYSTIN) CPUTIN (AUXTIN) CPUD-(AGND)
AGND
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
7.3.3.3. Monitor Temperature from Thermal Diode (Current Mode) The W83627DHG can also sense the diode temperature through Current Mode and the circuit is shown in the following figure.
W83627DHG
D+ Thermal Diode C=2200pF DCPUD-(AGND) (SYSTIN) CPUTIN (AUXTIN)
The pin of processor D- is connected to CPUD-(pin 105) and the pin D+ is connected to temperature sensor pin in the W83627DHG. A bypass capacitor C=2200pF should be added to filter the high frequency noise.
7.4
SST Command Summary
The W83627DHG is equipped with a built-in voltage and temperature sensor which uses the Simple Serial Transport (SST) interface. The sensor provides a means for an analog signal to travel over a digital bus enabling remote voltage and temperature sensing in areas previously not monitored in the PC. SST is a self-clocked, one-wire bus for data transfer. The bus requires no additional control lines. In addition, SST also includes variable data transfer rate established with every message. Therefore, it is comparatively flexible. The W83627DHG has a programmable SST address defined at Logical Device C CR[F1h]. The default address is 0x48h which is within the range of 0x48h-0x4ah defined in the SST specification.
7.4.1
Command Summary
The W83627DHG supports SST commands as shown in the following table:
COMMAND DESCRIPTION
GetIntTemp() GetExtTemp() GetAllTemps() GetVolt12V() GetVolt5V() GetVolt3p3V()
Returns the 2-byte temperature data values for pin SYSTIN(Pin 104) Returns the 2-byte temperature data values for pin CPUTIN(Pin 103) Returns the 4-byte temperature data values for both SYSTIN and CPUTIN Returns the 2-byte voltage data values for pin VIN0 (Pin 99). This pin should be connected to +12V power through scaling resistors Refer to 7.4.2.2 Returns the 2-byte voltage data values for pin VIN1 (Pin 98). This pin should be connected to +5V power through scaling resistors Refer to 7.4.2.2 Returns the 2-byte voltage data values for pin 3VCC (Pin 12, 28, 48).This pin should be connected to +3.3V power directly Refer to 7.4.2.2
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
Command Summary, continued.
COMMAND
DESCRIPTION
GetVolt2p5V() GetVoltVccp() GetAllVoltages()
Returns the 2-byte voltage data values for pin VIN2 (Pin 97). This pin should be connected to +2.5V power through scaling resistors. Refer to 7.4.2.2 Returns the 2-byte voltage data values of CPUVCORE (Pin 100). This pin should be connected to CPU power supply directly. The CPU power supply voltage must not be higher than 2.048 volt Returns a 10-byte voltage data value containing all the above listed five (5) voltages
7.4.2
Combination Sensor Data Format
7.4.2.1. Temperature Data Format The W83627DHG temperature data format of both CPUTIN and SYSTIN is 16-bit two's-complement binary value. It represents multiple of 1/64C in the temperature reading. Table 1 shows some typical temperature values in 16-bit two's complement format.
Table 1 Typical Temperature Values
TEMPERATURE
16-BIT DIGITAL OUTPUT (TWO'S COMPLEMENT) 16-BIT BINARY 16-BIT HEX
+80C +79.5C +1C +0C -1C -5C
0001 0100 0000 0000 0001 0011 1110 0000 0000 0000 0100 0000 0000 0000 0000 0000 1111 1111 1100 0000 1111 1110 1100 0000
1400h 13E0h 0010h 0000h FFC0h FEC0h
7.4.2.2. Voltage Data Format The W83627DHG can return five (5) voltage values through the SST interface. The voltage data format is 16-bit two's-complement binary. The relation between the 2-byte data and the monitored voltage is listed below: 1) CPUVCORE (pin 100) = Decimal[2-byte data by GetVoltVccp() ] / 1024 volts 2) 3VCC (pin 12) = Decimal[2-byte data by GetVolt3p3V()] / 1024 volts 3) "+12V" = Decimal[2-byte data by GetVolt12V()] / 1024 / ((R1+R2) / R2) volts VIN0 (pin 99) is connected as shown below:.
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
R2 +12V R1 150K 1% 10K 1% VIN0
4) "+5VCC" = Decimal[2-byte data by GetVolt5V()] / 1024 / ((R3+R4) / R4) volts VIN1 (pin 98) is connected as shown below:
R3 5VCC 30K 1% R4 10K 1% VIN1
5) "+2.5V" = Decimal[2-byte data by GetVolt2p5V()] / 1024 / ((R5+R6) / R6) volts VIN2 (pin 97) is connected as shown below:
R5 2.5V 10K 1% R6 10K 1% VIN2
7.5
PECI
PECI (Platform Environment Control Interface) is a proprietary derivation of SST. It is one of the temperature sensing methods that the W83627DHG supports. With a bandwidth ranging from 2 kbps to 2 Mbps, the PECI uses a single wire - no additional control lines needed - for self-clocking and data transfer. By interfacing to the Digital Thermal Sensor on the Intel(R) CPU, PECI reports a negative temperature value relative to the processor's temperature at which the thermal control circuit (TCC) is activated. To enable the PECI functionalities of the W83627DHG, BIOS/Software should follow the steps below: 1. Program Logical Device C, CR[E8h] bit (1..0) for PECI speed selection to meet the bit timing limits of CPU with PECI function. We recommend this bit is set to "11" for better stability. 2. Program Logical Device C, CR[E5h] bit (7..4) for each PECI Agent to match the number of domains in the processors. Setting to "1" enables the W83627DHG to issue GetTemp(0) and GetTemp(1) commands to access the PECI temperatures of domain 0 and domain 1. Setting to "0" enables the W83627DHG to issue GetTemp(0) command for domain 0. 3. Program Logical Device C, CR[E0] bit (3..0) for each PECI Agent. Setting to "1" returns the PECI temperature of domain 1 to the temperature reading register. Setting to "0" returns the PECI temperature of domain 0 to the temperature reading register. If CR[E5] bit 1 is set to "1", the higher PECI temperature of domain 0 and domain 1 is returned to the temperature reading register. See the example below for more details about the temperature reading register(s) 4. Program Logical Device C, CR[E0h] bit (7..4) for each PECI Agent. Setting to "1" enables the W83627DHG to access the agent. The power-on default is disabled. After an agent is enabled, the W83627DHG issues PING and GetTemp commands to obtain the PECI temperature
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
5. Since the PECI temperature is a relative value, the W83627DHG provides registers for each PECI Agent to convert the relative value to a more traditional "absolute" format. The TBase registers (Logical Device C, CR[E1h]~CR[E4h]) store the "base" temperature. By means of BIOS/software, the desired base temperature can be written to these registers. Important: the value must be positive. Otherwise abnormal temperature responses will take place. Here is an example on how to obtain TBase value: (1). Use a digital thermometer on the surface of the PECI processor to measure the processor body temperature. (2). Power up the system the PECI processor. Run the processor to 100% loading. (3). After the system is stable, read the PECI reading from Logical Device C, CR[FEh] and CR[FFh] and record the value of digital thermometer. (4). Calculate TBase. For example, if PECI = -10 and the digital thermometer is 50'C, then TBase could be set to 60'C. ( 60 - 10 = 50 ). 6. There are two temperature reading registers in the W83627DHG: CPUTIN (Bank1 Index 50h & 51h) and AUXTIN (Bank2 Index 50h & 51h). The source of the CPUTIN value is determined by the value programmed into the CPUFANOUT0 monitor Temperature source select register (Hardware Monitor Device, Bank 0, Index 49h, bits (2..0)). The source of AUXTIN value is determined by the value programmed into the AUXFANOUT monitor Temperature source select register (Hardware Monitor Device, Bank 0, Index 49h, bits(6..4)) 7. The temperature values in CPUTIN and AUXTIN are: CPUTIN = (TBase) + (PECI Agent relative temperature) AUXTIN = (TBase) + (PECI Agent relative temperature) Example: If the PECI relative temperature of agent 1 is -10; TBase is set to 72C, and Bank0 Index 49h selects PECI Agent 1 as the temperature source, the reported temperature will be 62C (-10 + 72). Please be noted that when the temperature source is selected as PECI, the CPUTIN or AUXTIN register reading does not reflect the actual temperature of processor. 8. In addition, the W83627DHG provides a PECISB pin that can be connected to a PECI host (e.g. chipset), so the W83627DHG becomes a bridge between that PECI host and the PECI client (e.g. CPU with PECI function). The bridge can pass the CPU PECI signals by programming Configure Register at Logical Device C, CR[E5h] Bit 0. An illustration is provided below (ICH8 is the alternative PECI host).
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
W83627DHG CPU PECISB PECI Host (Programmable Pass-through)
PECI
PECI
Fan Control LPC
ICH8
PECI Host
Fan Control
9. A warning flag register at Logical Device C, CR[E8h] bit (7..4) is designed for each PECI Agent to report whether the W83627DHG (PECI host) detects the PECI client or not and whether the PECI client returns invalid FCS values from the polling for three successive times.
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
7.6 Fan Speed Measurement and Control
This section is divided into two parts, one to measure the speed and one to control the speed.
7.6.1
Fan Speed Measurement
The W83627DHG can measure fan speed for fans equipped with tachometer outputs. The tachometer signals should be set to TTL-level, and the maximum input voltage cannot exceed +3.3 V. If the tachometer signal exceeds +3.3 V, an external trimming circuit should be added to reduce the voltage accordingly. The fan speed counter is read from Bank0 Index 28h, 29h, 2Ah, and 3Fh and Bank5 Index 53h. The fan speed can then be evaluated by the following equation:
RPM =
1.35 x 10 6 Count x Divisor
The default divisor is 2 and is specified at Bank0 Index 47h, bits 7 ~ 4; Index 4Bh, bits 7 ~ 6; Index 4Ch, bit 7; Index 59h, bit 7 and bits 3 ~ 2; and Index 5Dh, bits 5 ~ 7. There are three bits for each divisor, and the corresponding divisor is listed in the table below.
BIT 2 BIT 1 BIT 0 FAN DIVISOR BIT 2 BIT 1 BIT 0 FAN DIVISOR
0 0 0 0
0 0 1 1
0 1 0 1
1 2 4 8
1 1 1 1
0 0 1 1
0 1 0 1
16 32 64 128
The following table provides some examples of the relationship between divisor, RPM, and count.
NOMINAL RPM TIME PER REVOLUTION
DIVISOR
COUNTS
70% RPM
TIME FOR 70%
1 2 (default) 4 8 16 32 64 128
8800 4400 2200 1100 550 275 137 68
6.82 ms 13.64 ms 27.27 ms 54.54 ms 109.08 ms 218.16 ms 436.32 ms 872.64 ms
153 153 153 153 153 153 153 153
6160 3080 1540 770 385 192 96 48
9.84 ms 19.48 ms 38.96 ms 77.92 ms 155.84 ms 311.68 ms 623.36 ms 1246.72 ms
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
7.6.2 Fan Speed Control
The W83627DHG has four output pins for fan control, each of which offers PWM duty cycle and DC voltage to control the fan speed. The output type (PWM or DC) of each pin is configured by Bank0 Index 04h, bits 1 ~ 0; Index 12h, bit 0; and Index 62h, bit 6. For PWM, the duty cycle is programmed by eight-bit registers at Bank0 Index 01h, Index 03h, Index 11h and Index 61h. The duty cycle can be calculated using the following equation:
Dutycycle(%) =
Programmed 8 - bit Register Value x 100% 255
The default duty cycle is FFh, or 100%. The PWM clock frequency is programmed at Bank0 Index 00h, Index 02h, Index 10h and Index 60h. For DC, the W83627DHG has a six bit digital-to-analog converter (DAC) that produces 0 to 3.3 Volts DC. The analog output is programmed at Bank0 Index 01h, Index 03h, Index 11h and Index 61h. The analog output can be calculated using the following equation:
= AVCC OUTPUT Voltage (V) x
Programmed 6 - bit Register Value 64
The default value is 111111YY, or nearly 3.3 V, and Y is a reserved bit.
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
7.6.3 SMART FANTM Control
The W83627DHG supports two SMART FANTM I features--Thermal CruiseTM mode and Fan Speed CruiseTM mode--and SMART FANTM III. Each of these is discussed in the following sections. When enabling SMART FANTM I features, fan output starts from the previous setting in Bank0 Index 01h, Index 03h, Index 11h and Index 61h There are four pairs of temperature sensors and fan outputs in SMART FANTM I, it is illustrated in the figure below. SYSTIN CPUTIN PECI_Agent1 PECI_Agent2 PECI_Agent3 PECI_Agent4 Pin 116 SYSFANOUT
Pin 115 CPUFANOUT0 Pin 7 AUXFANOUT
AUXTIN PECI_Agent1 PECI_Agent2 PECI_Agent3 PECI_Agent4
Pin 120 CPUFANOUT1
SYSTIN CPUTIN AUXTIN PECI_Agent1 PECI_Agent2 PECI_Agent3 PECI_Agent4
7.6.3.1. Thermal CruiseTM Mode Four pairs of temperature sensors and fan outputs in Thermal CruiseTM mode: * SYSTIN and SYSFANOUT * CPUFANOUT0 and the temperature sensor selected by Bank0 Index 49h, bits 2 ~ 0 * AUXFANOUT and the temperature sensor selected by Bank0 Index 49h, bits 6 ~ 4 * CPUFANOUT1 and the temperature sensor selected by Bank0 Index 4Ah, bits 7 ~ 5
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
Thermal CruiseTM mode controls the fan speed to keep the temperature in a specified range. First, this range is defined in BIOS by a temperature and the interval (e.g., 55 C 3 C). As long as the current temperature remains below the low end of this range (i.e., 52 C), the fan is off. Once the temperature exceeds the low end, the fan turns on at a speed defined in BIOS (e.g., 20% output). Thermal CruiseTM mode then controls the fan output according to the current temperature. Three conditions may occur: (1) If the temperature still exceeds the high end, fan output increases slowly. If the fan is operating at full speed but the temperature still exceeds the high end, a warning message is issued to protect the system. (2) If the temperature falls below the high end (i.e., 58 C) but remains above the low end (e.g., 52 C), fan output remains the same. (3) If the temperature falls below the low end (e.g., 52 C), fan output decreases slowly to zero or to a specified "stop value". This stop value is enabled by Bank0 Index 12h, bits 3 ~ 5, and the value itself is specified in Bank0 Index 08h, Index 09h, Index 15h, and Index 64h. The fan remains at the stop value for the period of time defined in Bank0 Index 0Ch, Index 0Dh, Index 17h, and Index 66h. In general, Thermal CruiseTM mode means * if the current temperature is higher than the high end, increase the fan speed; * if the current temperature is lower than the low end, decrease the fan speed; * otherwise, keep the fan speed the same. The following figures illustrate two examples of Thermal CruiseTM mode.
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
7.6.3.2. Fan Speed CruiseTM Mode Four pairs of fan input sensors and fan outputs in Fan Speed CruiseTM mode. * SYSFANIN and SYSFANOUT * CPUFANIN0 and the temperature sensor selected by Bank0 Index 49h, bits 2 ~ 0 * AUXFANOUT and the temperature sensor selected by Bank0 Index 49h, bits 6 ~ 4 * CPUFANOUT1 and the temperature sensor selected by Bank0 Index 4Ah, bits 7 ~ 5 Fan Speed CruiseTM mode keeps the fan speed in a specified range. First, this range is defined in BIOS by a fan speed count (the amount of time between clock input signals, not the number of clock input signals in a period of time) and an interval (e.g., 160 10). As long as the fan speed count is in the specified range, fan output remains the same. If the fan speed count is higher than the high end (e.g., 170), fan output increases to make the count lower. If the fan speed count is lower than the low end (e.g., 150), fan output decreases to make the count higher. One example is illustrated in this figure.
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
A
Count 170 160 150 (%) 100 50 0
C
Fan output
The following tables show current temperatures, fan output values and the relative control registers at Thermal CruiseTM and Fan Speed CruiseTM mode. Display Registers - at SMART FANTM I Mode
DESCRIPTION REGISTER ADDRESS REGISTER NAME ATTRIBUTE BIT DATA
Current CPU Temperature Current SYS Temperature Current AUX Temperature Current CPUFANOUT0 Output Value Current SYSFANOUT Output Value Current AUXFANOUT Output Value Current CPUFANOUT1 Output Value
Bank1 Index 50h ,51h Bank 0 Index 27h Bank2 Index 50h,51h Bank0 Index 03h Bank0 Index 01h Bank0 Index 11h Bank0 Index 61h
CPUTIN Temperature Sensor SYSTIN Temperature Sensor AUXTIN Temperature Sensor CPUFANOUT0 Output Value Select SYSFANOUT Output Value Select AUXFANOUT Output Value Select CPUFANOUT1 Output Value Select
Read only Read only Read only 80h / FFh by strapping
8 MSB, 1C bit 7, 0.5 C 8 MSB, 1C 8 MSB, 1C bit 7, 0.5 C bits 7~0 CPUFANOUT0 Value bits 7~0 SYSFANOUT Value bits 7~0 AUXFANOUT Value bits 7~0 CPUFANOUT1 Value
FFh
FFh
80h / FFh by strapping
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
Relative Registers - at Thermal CruiseTM Mode
THERMAL-CRUI TM SE MODE TARGET TEMPERATURE START-UP STOP VALUE VALUE
Bank0, 0Ah Bank0, 0Bh Bank0, 16h Bank0, 65h Bank0, 08h Bank0, 09h Bank0, 15h Bank0, 64h
TOLERANCE
KEEP MIN. FAN OUTPUT VALUE
Bank0, 12h, Bit5 Bank0, 12h, Bit4 Bank0, 12h, Bit3 Bank0, 12h, Bit6
STOP TIME
Bank0, 0Ch Bank0, 0Dh Bank0, 17h Bank0, 66h
STEPDOWN TIME
STEP-UP TIME
SYSFANOUT CPUFANOUT0 AUXFANOUT CPUFANOUT1
Bank0, 05h Bank0, 06h Bank0, 13h Bank0, 63h
Bank0, 07h Bit0-3 Bank0, 07h, Bit4-7 Bank0, 14h, Bit0-3 Bank0, 62h, Bit0-3
Bank0, 0Eh
Bank0, 0Fh
Relative Registers-at Fan Speed CruiseTM Mode
SPEED CRUISETM MODE TARGET-SPEED COUNT TOLERANCE KEEP MIN. FAN OUTPUT VALUE STEP-DOWN TIME STEP-UP TIME
SYSFANOUT
Bank0, Index 05h
Bank0, Index 07h, bits 0-3 Bank0, Index 07h, bits 4-7 Bank0, Index 14h, bits 0-3 Bank0, Index 62h, bits 0-3
Bank0, Index 12h, Bit5 Bank0, Index 12h, Bit4 Bank0, Index 12h, Bit3 Bank0, Index 12h, Bit6
CPUFANOUT0
Bank0, Index 06h
Bank0, Index Bank0, 0Eh Index 0Fh
AUXFANOUT
Bank0, Index 13h
CPUFANOUT1
Bank0, Index 63h
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
7.6.3.3. SMART FANTM III SMART FANTM III controls the fan speed so that the temperature meets the target temperature set in BIOS or application software. There are only two pairs of fan outputs and temperature sensors in SMART FANTM III mode. * CPUFANOUT0 and the temperature sensor selected by Bank0 Index 49h, bits 2 ~ 0 * CPUFANOUT1 and the temperature sensor selected by Bank0 Index 4Ah, bits 7 ~ 5
CPUTIN PECI_Agent1 PECI_Agent2 PECI_Agent3 PECI_Agent4
Pin 115 CPUFANOUT0
SYSTIN AUXTIN CPUTIN PECI_Agent1 PECI_Agent2 PECI_Agent3 PECI_Agent4
Pin 120 CPUFANOUT1
The algorithm is as follows: (1) The target temperature, temperature tolerance, maximum and minimum fan outputs and step are set. (2) The following figure shows the initial conditions. If the current temperature is within (Target Temperature Temperature Tolerance), the fan speed remains constant.
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
Setting
Fan output (DC / PWM)
Max. Fan Output
Tolerance
Min. Fan Output Tar. - Tol. Tar. + Tol.
Temperature
(3) If the current temperature is higher than (Target Temperature + Temperature Tolerance), fan speed rises one step. The step is the value in the CPUFANOUT Output Value Select Register, Bank0 Index 03h or Index 61h. In addition, the target temperature shifts to (Target Temperature + Temperature Tolerance), creating a new target temperature, named Target Temperature 1 in this figure.
Current Temp. > Target Temp. +
Fan output (DC / PWM)
Max. Fan Output
Tolerance
Tol.
Step Fan Initial Output Value Min. Fan Output
Tar
Tar 1
Tar 3 Tar 2 Tar 4
Tar 5
Temperature
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
If the current temperature rises higher than (Target Temperature 1 + Temperature Tolerance), the fan speed rises one step again, and the target temperature shifts to (Target Temperature 1 + Temperature Tolerance), or Target Temperature 2. This process repeats whenever the current temperature is higher than (Target Temperature X Temperature Tolerance) or until the fan speed reaches its maximum speed. (4) If the current temperature falls below (Target Temperature Temperature Tolerance), the fan speed falls one step. The step is the value in the CPUFANOUT Output Value Select Register, Bank0 Index 03h or Index 61h. In addition, the target temperature shifts to (Target Temperature Temperature Tolerance), creating a new target temperature named Target Temperature 1.This is illustrated in the figure below.
Current Temp. < Target Temp. - Tol.
Fan output (DC / PWM)
Max. Fan Output Tolerance
Fan Initial Output Value Step Min. Fan Output
Tar 3
Tar 2 Tar 1
Tar
Temperature
If the current temperature falls lower than (Target Temperature 1 Temperature Tolerance), the fan speed is reduced one step again, and the target temperature shifts to (Target Temperature 1 Temperature Tolerance), or Target Temperature 2. This process repeats whenever the current temperature is lower than (Target Temperature X Temperature Tolerance) or until the fan speed reaches its minimum speed. (5) If the current temperature is always lower than (Target Temperature X Temperature Tolerance), the fan speed decreases slowly to zero or to a specified stop value. The stop value is enabled by register Bank0 Index 12h, bit 4 and bit 6, and the stop value is specified in Bank0 Index 09h and Index 64h. The fan remains at the stop value for the period of time defined in Bank0 Index 0Dh and Index 66h.
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
The following tables show current temperatures, fan output values and the relative control registers at SMART FANTM III mode. Display Register- at SMART FANTM III Mode
DESCRIPTION REGISTER ADDRESS REGISTER NAME ATTRIBUTE BIT DATA
Current CPU Temperature Current SYS Temperature Current AUX Temperature Current CPUFANOUT0 Output Value Current CPUFANOUT1 Output Value
Bank1 Index 50h ,51h Bank 0 Index 27h Bank2 Index 50h,51h Bank0 Index 03h Bank0 Index 61h
CPUTIN Temperature Sensor SYSTIN Temperature Sensor AUXTIN Temperature Sensor CPUFANOUT0 Output Value Select CPUFANOUT1 Output Value Select
Read only Read only Read only 80h / FFh by strapping 80h / FFh by strapping
8 MSB, 1C bit 7, 0.5 C 8 MSB, 1C 8 MSB, 1C bit 7, 0.5 C bits 7~0 CPUFANOUT0 Value bits 7~0 CPUFANOUT1 Value
Relative Register-at SMART FANTM III Control Mode
SMART FANTM III MODE CPUFANOUT0 CPUFANOUT1 SMART FANTM III MODE CPUFANOUT0 CPUFANOUT1 TARGET TEMPERATURE Bank0, Index 06h Bank0, Index 63h TOLERANCE Bank0, Index 07h, bits 4-7 Bank0, Index 62h, bits 0-3 STEP DOWN TIME STOP VALUE (MIN. FAN OUTPUT) Bank0, Index 09h Bank0, Index 64h STEP UP TIME MAX. FAN OUTPUT Bank0, Index 67h Bank0, Index 69h KEEP MIN. FAN OUTPUT VALUE Bank0, Index 12h, bit 4 Bank0, Index 12h, bit 6 STOP TIME Bank0, Index 0Dh Bank0, Index 66h
OUTPUT STEP
Bank0, Index 68h Bank0, Index 6Ah
Bank0, Index 0Eh
Bank0, Index 0Fh
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
7.7
7.7.1
Interrupt Detection
SMI# Interrupt Mode
The SMI#/OVT# pin (pin 5) is a multi-function pin. It can be in SMI# mode or in OVT# mode by setting Configuration Register CR[29h], bit 6 to one or zero, respectively. In SMI# mode, it can monitor voltages, fan counts, or temperatures. 7.7.1.1. Voltage SMI# Mode The SMI# pin can create an interrupt if a voltage exceeds a specified high limit or falls below a specified low limit. This interrupt must be reset by reading all the interrupt status registers, or subsequent events do not generate interrupts. This mode is illustrated in the following figure.
High limit
Low limit
Fan Count limit
SMI#
*
*
*
*
SMI#
*
*
*Interrupt Reset when Interrupt Status Registers are read
7.7.1.2. Fan SMI# Mode The SMI# pin can create an interrupt if a fan count crosses a specified fan limit (rises above it or falls below it). This interrupt must be reset by reading all the interrupt status registers, or subsequent events do not generate interrupts. This mode is illustrated in the figure above. 7.7.1.3. Temperature SMI# Mode The SMI# pin can create interrupts that depend on the temperatures measured by SYSTIN, CPUTIN, and AUXTIN. These interrupts are divided into two parts, one for SYSTIN and the other for CPUTIN / AUXTIN. 7.7.1.3.1. Temperature Sensor 1(SYSTIN) SMI# Interrupt The SMI# pin has three interrupt modes with SYSTIN. (1) Comparator Interrupt Mode This mode is enabled by setting THYST (Temperature Hysteresis) to 127C. In this mode, the SMI# pin can create an interrupt as long as the current temperature exceeds TO (Over Temperature). This interrupt can be reset by reading all the interrupt status registers, or subsequent events do not generate interrupts. If the interrupt is reset, the SMI# pin continues to create interrupts until the temperature goes below TO. This is illustrated in the figure below.
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T HYST 127'C
T OI
T OI
T HYST
SMI#
*
*
*
*
SMI#
*
*
*
*Interrupt Reset when Interrupt Status Registers are read
Comparator Interrupt Mode Mode
Two-Time Interrupt
(2) Two-Time Interrupt Mode This mode is enabled by setting THYST (Temperature Hysteresis) lower than TO and setting Bank0 Index 4Ch, bit 5 to zero. In this mode, the SMI# pin can create an interrupt when the current temperature rises above TO or when the current temperature falls below THYST. Once the temperature rises above TO, however, and generates an interrupt, this mode does not generate additional interrupts, even if the temperature remains above TO, until the temperature falls below THYST. This interrupt must be reset by reading all the interrupt status registers, or subsequent events do not generate interrupts. This is illustrated in the figure above. (3) One-Time Interrupt Mode This mode is enabled by setting THYST (Temperature Hysteresis) lower than TO and setting Bank0 Index 4Ch, bit 5 to one. In this mode, the SMI# pin can create an interrupt when the current temperature rises above TO. Once the temperature rises above TO, however, and generates an interrupt, this mode does not generate additional interrupts, even if the temperature remains above TO, until the temperature falls below THYST. This interrupt must be reset by reading all the interrupt status registers, or subsequent events do not generate interrupts. This is illustrated in the following figure.
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T OI
T HYST
SMI#
*
*
*Interrupt Reset when Interrupt Status Registers are read
One-Time Interrupt Mode 7.7.1.3.2. Temperature Sensor 2(CPUTIN) And Sensor 3(AUXTIN) SMI# Interrupt The SMI# pin has two interrupt modes with CPUTIN / AUXTIN. (1) Comparator Interrupt Mode This mode is enabled by setting Bank0 Index 4Ch, bit 6, to one. In this mode, the SMI# pin can create an interrupt when the current temperature exceeds TO (Over Temperature) and continues to create interrupts until the temperature falls below THYST. This interrupt can be reset by reading all the interrupt status registers, or subsequent events do not generate interrupts. This is illustrated in the figure below.
T OI
T OI
T HYST
T HYST
SMI#
*
*
*
*
*
SMI#
*
*
*
*Interrupt Reset when Interrupt Status Registers are read
Comparator Interrupt Mode Interrupt Mode
Two-Time
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Publication Release Date: Aug, 22, 2007 Version 1.4
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(2) Two-Times Interrupt Mode This mode is enabled by setting Bank0 Index 4Ch, bit 6, to zero. In this mode, the SMI# pin can create an interrupt when the current temperature rises above TO or when the current temperature falls below THYST. Once the temperature rises above TO, however, and generates an interrupt, this mode does not generate additional interrupts, even if the temperature remains above TO, until the temperature falls below THYST. This interrupt must be reset by reading all the interrupt status registers, or subsequent events do not generate interrupts. This is illustrated in the figure above.
7.7.2
OVT# Interrupt Mode
The SMI#/OVT# pin is a multi-function pin. It can be in SMI# mode or in OVT# mode by setting Configuration Register CR[29h], bit 6 to one or zero, respectively. In OVT# mode, it can monitor temperatures, and it is enabled or disabled for SYSTIN, CPUTIN, and AUXTIN by Bank0 Index 18h, bit 6; Bank0 Index 4Ch, bit 3; and Bank0 Index 4Ch, bit4. The OVT# pin has two interrupt modes, comparator and interrupt. The modes are illustrated in this figure.
To
T HYST
OVT#
(Comparator Mode; default)
OVT#
(Interrupt Mode)
*
*
*
*Interrupt Reset when Temperature sensor registers are read
If Bank0 Index 18h, bit 4, Bank1 Index 52h, bit 1, and Bank2 Index 52h, bit1 are set to zero, the OVT# pin is in comparator mode. In comparator mode, the OVT# pin can create an interrupt once the current temperature exceeds TO and continues to create interrupts until the temperature falls below THYST. The OVT# pin is asserted once the temperature has exceeded TO and has not yet fallen below THYST. If Bank0 Index 18h, bit 4, Bank1 Index 52h, bit1, and Bank2 Index 52h, bit 1 are set to one, the OVT# pin is in interrupt mode. In interrupt mode, the OVT# pin can create an interrupt once the current temperature rises above TO or when the temperature falls below THYST. Once the temperature rises above TO, however, and generates an interrupt, this mode does not generate additional interrupts, even if the temperature remains above TO, until the temperature falls below THYST. This interrupt must be reset by reading all the interrupt status registers. The OVT# pin is asserted when an interrupt is generated and remains asserted until the interrupt is reset.
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7.7.3 Caseopen Detection
The purpose of Caseopen function is used to detect whether the computer case is opened. This feature must be able to function even when there is no 3VSB power. Consequently, the power source for the circuit is from either Pin 74 (VBAT) or Pin 61 (3VSB). 3VSB is the default power source. If there is no 3VSB power, the power source is VBAT. This is designed to save power consumption of the battery. When the case is closed, the signal of Pin 76 must be pulled high by an externally pulled-up 2M resistor that is connected to Pin 74. Once the case is opened, the signal will be changed from high to low. Meanwhile, the detection circuit inside the IC latches the signal. As a result, the interrupt status and the real-time status can be read at the registers next time when the computer is booted. The status will not be cleared unless Bank 0, Index 46h, bit 7, or CR[E6h] bit 5 at Logical Device A is set to "1" first and then to "0".
CASEOPEN# CASEOPEN CLEAR CASEOPEN STATUS
Figure 7.1 Caseopen Logic
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Publication Release Date: Aug, 22, 2007 Version 1.4
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7.7.4 BEEP Alarm Function
The W83627DHG provides an alarm output function at the BEEP/SO pin. The BEEP/SO pin is a multi-function pin and can be configured as BEEP output, if Configuration Register CR[24h], bit 1 is set to zero. The BEEP outputs a warning tone when one of the monitored parameters in the following events is out of the preset range. Any voltage input of the nine pins (CPUVCORE, VIN[0..3], 3VCC, AVCC , 3VSB and VBAT) is out of the allowed range; Any temperature input of the three pins (SYSTIN, CPUTIN and AUXTIN) exceeds the limit; Any fan input of the five pins (SYSFANIN, CPUFANIN0, AUXFANIN0, CPUFANIN1 and AUXFANIN1) exceeds the limit; CASEOPEN# input pin is sampled low; User-defined bit (Bank 4, Index 53h, bit 5) is written to 1. Whether the BEEP alarm function is enabled or disabled is determined by the control bit at Hardware Monitor Device, Bank 0, Index 57h, bit 7. Also, each event has their individual enable bit at Hardware Monitor Device, Bank 0, Index 56h bit[7:0], Index 57h bit[6:0] and Bank 4, Index 53h, bit[1:0]. BEEP/SO is an open-drain output pin and its default state is low. When the BEEP alarm function is activated, this pin repeatedly outputs 600 Hz square wave for 0.5 second and 1.2 KHz square wave for 0.5 second in turn until the enable bit or the abnormal event is cleared.
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8. HARDWARE MONITOR REGISTER SET
The base address of the Address Port and Data Port is specified in registers CR60 and CR61 of Device B, the hardware monitor device. CR60 is the high byte, and CR61 is the low byte. The Address Port and Data Port are located at the base address, plus 5h and 6h, respectively. For example, if CR60 is 02h and CR61 is 90h, the Address Port is at 0x295h, and the Data Port is at 0x296h.
8.1
Address Port (Port x5h)
Port +5h 00h Bit 6:0 Read/write , Bit 7: Reserved 8 bits
7 6 5 4 3 2 1 0
Address Port: Power on Default Value Attribute: Size:
Data
Reserved
Bit7: Reserved Bit 6-0: Read/Write
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Reserved (Power On default 0) A6 A5
Address Pointer (Power On default 00h) A4 A3 A2 A1 A0
8.2
Data Port (Port x6h)
Port +6h 00h Read/Write 8 bits
7 6 5 4 3 2 1 0
Data Port: Power on Default Value Attribute: Size:
Data
Bit 7-0: Data to be read from or to be written to Value RAM and Register.
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8.3 SYSFANOUT PWM Output Frequency Configuration Register - Index 00h (Bank 0)
00h 04h Read/Write 8 bits
7 6 5 4 3 2 1 0
Register Location: Power on Default Value: Attribute: Size:
PWM_SCALE1
PWM_CLK_SEL1
The register is meaningful only when SYSFANOUT is programmed for PWM output (i.e.,
Bank0 Index 04h, bit 0 is 0). Bit 7: SYSFANOUT PWM Input Clock Source Select. This bit selects the clock source for PWM output frequency. 0: clock source is 24 MHz. 1: clock source is 180 KHz. Bit 6-0: SYSFANOUT PWM Pre-Scale divider. The clock source for PWM output is divided by this seven-bit value to calculate the actual PWM output frequency.
PWM output frequency =
Input Clock 1 Pre_Scale Divider 256
The maximum value of the divider is 127 (7Fh), and it should not be set to 0.
8.4
SYSFANOUT Output Value Select Register - Index 01h (Bank 0)
01h FFh Read/Write 8 bits
7 6 5 4 3 2 1 0
Register Location: Power on Default Value: Attribute: Size:
SYSFANOUT Value
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(1)If SYSFANOUT is programmed for PWM output (Bank0 Index 04h,bit0 is 0) Bit 7-0: The PWM duty cycle is equal to this eight-bit value, divided by 255, times 100%. FFh creates a duty cycle of 100%, and 00h creates a duty cycle of 0%. (2)If SYSFANOUT is programmed for DC Voltage output (Bank0 Index 04h,bit0 is 1) Bit 7-2: SYSFANOUT voltage control. The output voltage is calculated according to this equation. OUTPUT Voltage = AVCC * Bit 1-0: Reserved.
FANOUT 64
8.5
CPUFANOUT0 PWM Output Frequency Configuration Register - Index 02h (Bank 0)
02h 04h Read/Write 8 bits
7 6 5 4 3 2 1 0
Register Location: Power on Default Value: Attribute: Size:
PWM_SCALE2
PWM_CLK_SEL2
The register is meaningful only when CPUFANOUT0 is programmed for PWM output.
Bit 7: CPUFANOUT0 PWM Input Clock Source Select. This bit selects the clock source for PWM output. 0: clock source is 24 MHz. 1: clock source is 180 KHz. Bit 6-0: CPUFANOUT0 PWM Pre-Scale divider. The clock source for PWM output is divided by this seven-bit value to calculate the actual PWM output frequency.
PWM output frequency =
Input Clock 1 Pre_Scale Divider 256
The maximum value of the divider is 127 (7Fh), and it should not be set to 0.
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8.6 CPUFANOUT0 Output Value Select Register - Index 03h (Bank 0)
03h Strap by FAN_SET(Pin 117) Read/Write 8 bits
7 6 5 4 3 2 1 0
Register Location: Power on Default Value: Attribute: Size:
CPUFANOUT0 Value
(1)If CPUFANOUT0 is programmed for PWM output (Bank0 Index 04h,bit1 is 0) Bit 7-0: CPUFANOUT0 PWM Duty Cycle. The PWM duty cycle is equal to this eight-bit value, divided by 255, times 100%. FFh creates a duty cycle of 100%, and 00h creates a duty cycle of 0% (2)If CPUFANOUT0 is programmed for DC Voltage output (Bank0 Index 04h,bit1 is 1) Bit 7-2: CPUFANOUT0 voltage control. The output voltage is calculated according to this equation.
OUTPUT Voltage = AVCC * Bit 1-0: Reserved.
FANOUT 64
8.7
FAN Configuration Register I - Index 04h (Bank 0)
04h 01h Read/Write 8 bits
7 6 5 4 3 2 1 0
Register Location: Power on Default Value: Attribute: Size:
SYSFANOUT_SEL CPUFANOUT0_SEL SYSFANOUT_Mode SYSFANOUT_Mode CPUFANOUT0_Mode CPUFANOUT0_Mode Reserved Reserved
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Bit 7-6: Reserved Bit 5-4: CPUFANOUT0 mode control. 00: CPUFANOUT0 is in Manual Mode. (Default) 01: CPUFANOUT0 is in Thermal CruiseTM Mode. 10: CPUFANOUT0 is in Fan Speed CruiseTM Mode. 11: CPUFANOUT0 is in SMART FANTM III Mode. Bit 3-2: SYSFANOUT mode control. 00: SYSFANOUT is as Manual Mode. (Default) 01: SYSFANOUT is as Thermal CruiseTM Mode. 10: SYSFANOUT is as Fan Speed CruiseTM Mode. 11: Reserved and no function. Bit 1: CPUFANOUT0 output mode selection. 0: CPUFANOUT0 pin produces a PWM output duty cycle. (Default) 1: CPUFANOUT0 pin produces DC output. Bit 0: SYSFANOUT output mode selection. 0: SYSFANOUT pin produces a PWM duty cycle output. 1: SYSFANOUT pin produces DC output. (Default)
8.8
SYSTIN Target Temperature Register/ SYSFANIN Target Speed Register Index 05h (Bank 0)
05h 00h Read/Write 8 bits
5 4 3 2 1 0
Register Location: Power on Default Value: Attribute: Size:
7 6
Target Temperature / Target Speed
(1)In Thermal CruiseTM mode, Bit 7: Reserved. Bit 6-0: SYSTIN Target Temperature. (2)In Fan Speed CruiseTM mode, Bit 7-0: SYSFANIN Target Speed.
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8.9 CPUTIN Target Temperature Register/ CPUFANIN0 Target Speed Register Index 06h (Bank 0)
06h 00h Read/Write 8 bits
5 4 3 2 1 0
Register Location: Power on Default Value: Attribute: Size:
7 6
Target Temperature / Target Speed
(1)In Thermal CruiseTM mode or SMART FANTM III mode, Bit 7: Reserved. Bit 6-0: CPUTIN Target Temperature. (2)In Fan Speed CruiseTM mode, Bit 7-0: CPUFANIN0 Target Speed.
8.10 Tolerance of Target Temperature or Target Speed Register - Index 07h (Bank 0)
Register Location: Power on Default Value: Attribute: Size:
7 6 5
07h 00h Read/Write 8 bits
4 3 2 1 0
SYSTIN Target Temperature Tolerance / SYSFANIN Target Speed Tolerance CPUTIN Target Temperature Tolerance / CPUFANIN0 Target Speed Tolerance
(1)In Thermal CruiseTM mode or SMART FANTM III mode, Bit 7-4: Tolerance of CPUTIN Target Temperature. Bit 3-0: Tolerance of SYSTIN Target Temperature. (2)In Fan Speed CruiseTM mode, Bit 7-4: Tolerance of CPUFANIN0 Target Speed.
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Bit 3-0: Tolerance of SYSFANIN Target Speed.
8.11 SYSFANOUT Stop Value Register - Index 08h (Bank 0)
Register Location: Power on Default Value: Attribute: Size:
7 6
08h 01h Read/Write 8 bits
5 4 3 2 1 0
SYSFANOUT Stop Value
In Thermal CruiseTM mode, the SYSFANOUT value decreases to this eight-bit value if the temperature stays below the lowest temperature limit. This value should not be zero. Please note that Stop Value does not mean that the fan really stops. It means that if the temperature keeps below low temperature limit, then the fan speed keeps on decreasing until reaching a minimum value, and this is Stop Value.
8.12 CPUFANOUT0 Stop Value Register - Index 09h (Bank 0)
Register Location: Power on Default Value: Attribute: Size:
7 6
09h 01h Read/Write 8 bits
5 4 3 2 1 0
CPUFANOUT0 Stop Value
InThermal CruiseTM mode or SMART FANTM III mode, the CPUFANOUT0 value decreases to this eight-bit value if the temperature stays below the lowest temperature limit. This value should not be zero. Please note that Stop Value does not mean that the fan really stops. It means that if the temperature keeps below low temperature limit, then the fan speed keeps on decreasing until reaching a minimum value, and this is Stop Value.
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8.13 SYSFANOUT Start-up Value Register - Index 0Ah (Bank 0)
Register Location: Power on Default Value: Attribute: Size:
7 6
0Ah 01h Read/Write 8 bits
5 4 3 2 1 0
SYSFANOUT Start-up Value
In Thermal CruiseTM mode, SYSFANOUT value increases from zero to this eight-bit register value to provide a minimum value to turn on the fan.
8.14 CPUFANOUT0 Start-up Value Register - Index 0Bh (Bank 0)
Register Location: Power on Default Value: Attribute: Size:
7
0Bh 01h Read/Write 8 bits
6 5 4 3 2 1 0
CPUFANOUT0 Start-up Value
In Thermal CruiseTM mode, CPUFANOUT0 value increases from zero to this eight-bit register value to provide a minimum value to turn on the fan.
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8.15 SYSFANOUT Stop Time Register - Index 0Ch (Bank 0)
Register Location: Power on Default Value: Attribute: Size:
7 6
0Ch 3Ch Read/Write 8 bits
5 4 3 2 1 0
SYSFANOUT Stop Time
In Thermal CruiseTM mode, if the stop value is enabled, this register determines the amount of time it takes the SYSFANOUT value to fall from the stop value to zero. (1)For PWM output: The units are intervals of 0.1 seconds. The default time is 6 seconds. (2)For DC output: The units are intervals of 0.4 seconds. The default time is 24 seconds.
8.16 CPUFANOUT0 Stop Time Register - Index 0Dh (Bank 0)
Register Location: Power on Default Value: Attribute: Size:
7 6
0Dh 3Ch Read/Write 8 bits
5 4 3 2 1 0
CPUFANOUT0 Stop Time
In Thermal CruiseTM mode or SMART FANTM III mode, this register determines the amount of time it takes the CPUFANOUT0 value to fall from the stop value to zero. (1)For PWM output: The units are intervals of 0.1 seconds. The default time is 6 seconds. (2)For DC output: The units are intervals of 0.4 seconds. The default time is 24 seconds.
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Publication Release Date: Aug, 22, 2007 Version 1.4
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8.17 Fan Output Step Down Time Register - Index 0Eh (Bank 0)
Register Location: Power on Default Value: Attribute: Size:
7 6
0Eh 0Ah Read/Write 8 bits
5 4 3 2 1 0
FANOUT Value Step Down Time
In SMART FANTM mode, this register determines the amount of time it takes FANOUT to decrease its value by one step. (1)For PWM output: The units are intervals of 0.1 seconds. The default time is 1 seconds. (2)For DC output: The units are intervals of 0.4 seconds. The default time is 4 seconds.
8.18 Fan Output Step Up Time Register - Index 0Fh (Bank 0)
Register Location: Power on Default Value: Attribute: Size:
7 6
0Fh 0Ah Read/Write 8 bits
5 4 3 2 1 0
FANOUT Value Step Up Time
In SMART FANTM mode, this register determines the amount of time it takes FANOUT to increase its value by one step. (1)For PWM output: The units are intervals of 0.1 second. The default time is 1 second. (2)For DC output: The units are intervals of 0.4 second. The default time is 4 seconds.
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8.19 AUXFANOUT PWM Output Frequency Configuration Register - Index 10h (Bank 0)
Register Location: Power on Default Value: Attribute: Size: 10h 04h Read/Write 8 bits
7 6 5 4 3 2 1 0
PWM_SCALE3
PWM_CLK_SEL3
The register is only meaningful when AUXFANOUT is programmed for PWM output(i.e.,
Bank0 Index 12h, bit 0 is 0). Bit 7: AUXFANOUT PWM Input Clock Source Select. This bit selects the clock source of PWM output frequency. 0: clock source is 24 MHz. 1: clock source is 180 KHz. Bit 6-0: AUXFANOUT PWM Pre-Scale divider. The clock source for PWM output is divided by this seven-bit value to calculate the actual PWM output frequency. PWM output frequency =
Input Clock 1 Pre_Scale Divider 256
The maximum value of the divider is 127 (7Fh), and it should not be set to 0.
8.20 AUXFANOUT Output Value Select Register - Index 11h (Bank 0)
Register Location: Power on Default Value: Attribute: Size:
7
11h FFh Read/Write 8 bits
6 5 4 3 2 1 0
AUXFANOUT Value
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(1)If AUXFANOUT is programmed for PWM output (Bank0 Index 12h,bit0 is 0) Bit 7-0: AUXFANOUT PWM Duty Cycle. The PWM duty cycle is equal to this eight-bit value, divided by 255, times 100%. FFh creates a duty cycle of 100%, and 00h creates a duty cycle of 0%. (2)If AUXFANOUT is programmed for DC output (Bank0 Index 12h,bit0 is 1) Bit 7-2: AUXFANOUT voltage control. The output voltage is calculated according to this equation.
OUTPUT Voltage = Bit 1-0: Reserved.
AVCC *
FANOUT 64
8.21 FAN Configuration Register II - Index 12h (Bank 0)
Register Location: Power on Default Value: Attribute: Size:
7
12h 00h Read/Write 8 bits
6 5 4 3 2 1 0
AUXFANOUT_SEL AUXFANOUT_Mode AUXFANOUT_Mode AUXFANOUT_MIN_Value CPUFANOUT0_MIN_Value SYSFANOUT_MIN_Value CPUFANOUT1_MIN_Value Reserved
Bit 7: Reserved Bit 6: 0: CPUFANOUT1 value decreases to zero when the temperature goes below the target range. 1: CPUFANOUT1 value decreases to the value specified in Index 64h when the temperature goes below the target range. Bit 5: 0: SYSFANOUT value decreases to zero when the temperature goes below the target range. 1: SYSFANOUT value decreases to the value specified in Index 08h when the temperature goes below the target range. Bit 4: 0: CPUFANOUT0 value decreases to zero when the temperature goes below the target range. 1: CPUFANOUT0 value decreases to the value specified in Index 09h when the temperature goes below the target range. Bit 3: 0: AUXFANOUT value decreases to zero when the temperature goes below the target range. 1: AUXFANOUT value decreases to the value specified in Index 17h when the temperature goes below the target range. Publication Release Date: Aug, 22, 2007 Version 1.4
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Bit 2-1: AUXFANOUT mode control. 00: AUXFANOUT is in Manual Mode. (Default) 01: AUXFANOUT is in Thermal CruiseTM Mode. 10: AUXFANOUT is in Fan Speed CruiseTM Mode. 11: Reserved and no function. Bit 0: 0: AUXFANOUT pin produces a PWM output duty cycle. (Default) 1: AUXFANOUT pin produces DC output.
8.22 AUXTIN Target Temperature Register/ AUXFANIN0 Target Speed Register Index 13h (Bank 0)
Register Location: Power on Default Value: Attribute: Size:
7 6 5
13h 00h Read/Write 8 bits
4 3 2 1 0
Target Temperature / Target Speed
(1)In Thermal CruiseTM mode: Bit 7: Reserved. Bit 6-0: AUXTIN Target Temperature. (2)In Fan Speed CruiseTM mode: Bit 7-0: AUXFANIN0 Target Speed.
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8.23 Tolerance of Target Temperature or Target Speed Register - Index 14h (Bank 0)
Register Location: Power on Default Value: Attribute: Size:
7 6 5
14h 00h Read/Write 8 bits
4 3 2 1 0
AUXTIN Target Temperature Tolerance / AUXFANIN Target Speed Tolerance Reserved
(1)In Thermal CruiseTM mode: Bit 3-0: Tolerance of AUXTIN Target Temperature. (2)In Fan Speed CruiseTM mode: Bit 3-0: Tolerance of AUXFANIN0 Target Speed.
8.24 AUXFANOUT Stop Value Register - Index 15h (Bank 0)
Register Location: Power on Default Value: Attribute: Size:
7 6
15h 01h Read/Write 8 bits
5 4 3 2 1 0
AUXFANOUT Stop Value
In Thermal CruiseTM mode, the AUXFANOUT value decreases to this eight-bit value if the temperature stays below the lowest temperature limit. This value should not be zero. Please note that Stop Value does not mean that the fan really stops. It means that if the temperature keeps below low temperature limit, then the fan speed keeps on decreasing until reaching a minimum value, and this is Stop Value.
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8.25 AUXFANOUT Start-up Value Register - Index 16h (Bank 0)
Register Location: Power on Default Value: Attribute: Size:
7 6
16h 01h Read/Write 8 bits
5 4 3 2 1 0
AUXFANOUT Start-up Value
In Thermal CruiseTM mode, the AUXFANOUT value increases from zero to this eight-bit register value to provide a minimum value to turn on the fan.
8.26 AUXFANOUT Stop Time Register - Index 17h (Bank 0)
Register Location: Power on Default Value: Attribute: Size:
7 6
17h 3Ch Read/Write 8 bits
5 4 3 2 1 0
AUXFANOUT Stop Time
In Thermal CruiseTM mode, if the stop value is enabled, this register determines the amount of time it takes the AUXFANOUT value to fall from the stop value to zero. (1) For PWM output, The units are intervals of 0.1 second. The default time is 6 seconds. (2) For DC output, The units are intervals of 0.4 second. The default time is 24 seconds.
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8.27 OVT# Configuration Register - Index 18h (Bank 0)
Register Location: Power on Default Value: Attribute: Size: 18h 43h Read/Write 8 bits
7 6 5 4 3 2 1 0
Reserved Reserved Reserved Reserved OVT1_Mode Reserved DIS_OVT1 Reserved
Bit 7: Reserved. Bit 6: 0: Enable SYSTIN OVT# output. (Default) 1: Disable temperature sensor SYSTIN over-temperature (OVT#) output. Bit 5: Reserved. Bit 4: 0: Compare mode. (Default) 1: Interrupt mode. Bit 3-0: Reserved.
8.28 Reserved Registers - Index 19h ~ 1Fh (Bank 0) 8.29 Value RAM Index 20h ~ 3Fh (Bank 0)
ADDRESS A6-A0 DESCRIPTION
20h 21h 22h 23h 24h 25h 26h 27h 28h
29h
CPUVCORE reading VIN0 reading AVCC reading 3VCC reading VIN1 reading VIN2 reading VIN3 reading SYSTIN temperature sensor reading SYSFANIN reading Note: This location stores the number of counts of the internal clock per revolution. CPUFANIN0 reading Note: This location stores the number of counts of the internal clock per revolution.
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Value RAM Index 20h ~ 3Fh (Bank 0) , continued.
ADDRESS A6-A0
DESCRIPTION
2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh
3Ch
3Dh
3Eh
3Fh
AUXFANIN0 reading Note: This location stores the number of counts of the internal clock per revolution. CPUVCORE High Limit CPUVCORE Low Limit VIN0 High Limit VIN0 Low Limit AVCC High Limit AVCC Low Limit 3VCC High Limit 3VCC Low Limit VIN1 High Limit VIN1 Low Limit VIN2 High Limit VIN2 Low Limit VIN3 High Limit VIN3 Low Limit SYSTIN temperature sensor High Limit SYSTIN temperature sensor Hysteresis Limit SYSFANIN Fan Count Limit Note: It is the number of counts of the internal clock for the Limit of the fan speed. CPUFANIN0 Fan Count Limit Note: It is the number of counts of the internal clock for the Limit of the fan speed. AUXFANIN0 Fan Count Limit Note: It is the number of counts of the internal clock for the Limit of the fan speed. CPUFANIN1 Fan Count Limit Note: It is the number of counts of the internal clock for the Limit of the fan speed. CPUFANIN1 reading Note: This location stores the number of counts of the internal clock per revolution.
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8.30 Configuration Register - Index 40h (Bank 0)
Register Location: Power on Default Value: Attribute: Size: 40h 03h Read/Write 8 bits
7 6 5 4 3 2 1 0 START SMI#Enable Reserved INT_Clear Reserved Reserved Reserved INITIALIZATION
Bit 7: A one restores the power-on default values to some registers. This bit clears itself since the power-on default of this bit is zero. Bit 6-4: Reserved Bit 3: A one disables the SMI# output without affecting the contents of Interrupt Status Registers. The device will stop monitoring. It will resume upon clearing of this bit. Bit 2: Reserved Bit 1: A one enables the SMI# Interrupt output. Bit 0: A one enables startup of monitoring operations; a zero puts the part in standby mode. Note: The outputs of Interrupt pins will not be cleared if the user writes a zero to this location after an interrupt has occurred unlike "INT_Clear'' bit.
8.31 Interrupt Status Register 1 - Index 41h (Bank 0)
Register Location: Power on Default Value: Attribute: Size: 41h 00h Read Only 8 bits
7 6 5 4 3 2 1 0
CPUVCORE VIN0 AVCC(Pin95) 3VCC SYSTIN CPUTIN SYSFANIN CPUFANIN0
Bit 7: A one indicates the fan count limit of CPUFANIN0 has been exceeded. Bit 6: A one indicates the fan count limit of SYSFANIN has been exceeded. Bit 5: A one indicates the high limit of CPUTIN temperature has been exceeded. Publication Release Date: Aug, 22, 2007 Version 1.4
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Bit 4: A one indicates the high limit of SYSTIN temperature has been exceeded. Bit 3: A one indicates the high or low limit of 3VCC has been exceeded. Bit 2: A one indicates the high or low limit of AVCC has been exceeded. Bit 1: A one indicates the high or low limit of VIN0 has been exceeded. Bit 0: A one indicates the high or low limit of CPUVCORE has been exceeded.
8.32 Interrupt Status Register 2 - Index 42h (Bank 0)
Register Location: Power on Default Value: Attribute: Size: 42h 00h Read Only 8 bits
7 6 5 4 3 2 1 0
VIN1 VIN3 VIN2 AUXFANIN0 CASEOPEN AUXTIN TAR1 TAR2
Bit 7: A one indicates that the CPUTIN temperature has been over the target temperature for three minutes at full fan speed in Thermal CruiseTM mode. Bit 6: A one indicates that the SYSTIN temperature has been over the target temperature for three minutes at full fan speed in Thermal CruiseTM mode. Bit 5: A one indicates the high limit of AUXTIN temperature has been exceeded. Bit 4: A one indicates case has been opened. Bit 3: A one indicates the fan count limit of AUXFANIN0 has been exceeded. Bit 2: A one indicates the high or low limit of VIN2 has been exceeded. Bit 1: A one indicates the high or low limit of VIN3 has been exceeded. Bit 0: A one indicates the high or low limit of VIN1 has been exceeded.
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8.33 SMI# Mask Register 1 - Index 43h (Bank 0)
Register Location: Power on Default Value: Attribute: Size: 43h FFh Read/Write 8 bits
7 6 5 4 3 2 1 0
CPUVCORE VIN0 AVCC(Pin95) 3VCC SYSTIN CPUTIN SYSFANIN CPUFANIN0
Bit 7-0: A one disables the corresponding interrupt status bit for the SMI interrupt. (See Interrupt Status Register 1 - Index 41h (Bank 0))
8.34 SMI# Mask Register 2 - Index 44h (Bank 0)
Register Location: Power on Default Value: Attribute: Size: 44h FFh Read/Write 8 bits
7 6 5 4 3 2 1 0
VIN1 VIN3 VIN2 AUXFANIN0 CASEOPEN AUXTIN TAR1 TAR2
Bit 7-0: A one disables the corresponding interrupt status bit for the SMI interrupt. (See Interrupt Status Register 2 - Index 42h (Bank 0))
8.35 Reserved Register - Index 45h (Bank 0) 8.36 SMI# Mask Register 3 - Index 46h (Bank 0)
Register Location: Power on Default Value: Attribute: Size: 46h 07h Read/Write 8 bits
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7
6
5
4
3
2
1
0
Reserved CPUFANIN1 AUXFANIN1 Reserved Reserved Reserved Reserved CaseOpen Clear
Bit 7: CASEOPEN Clear Control. Write 1 to this bit will clear CASEOPEN status. This bit won't be self cleared, please write 0 after event be cleared. The function is the same as LDA, CR[E6h] bit 5. Bit 6-3: Reserved. Bit 2-1: A one disables the corresponding interrupt status bit for the SMI interrupt. (See Interrupt Status Register 3 - Index 50h (Bank 4)) Bit 0: Reserved.
8.37 Fan Divisor Register I - Index 47h (Bank 0)
Register Location: Power on Default Value: Attribute: Size:
7
47h 55h Read/Write 8 bits
6 5 4 3 2 1 0
FANINC5 FANOPV5 FANINC4 FANOPV4 SYSFANIN DIV_B0 SYSFANIN DIV_B1 CPUFANIN0 DIV_B0 CPUFANIN0 DIV_B1
Bit 7-6: CPUFANIN0 Divisor, bits1-0. (See VBAT Monitor Control Register - Index 5Dh (Bank 0)) Bit 5-4: SYSFANIN Divisor, bits1-0. (See VBAT Monitor Control Register - Index 5Dh (Bank 0)) Bit 3: CPUFANIN1 output value, only if bit 2 is set to zero. Otherwise, this bit has no meaning. 1: Pin119(CPUFANIN1) generates a logic-high signal. 0: Pin119 generates a logic-low signal. (Default) Bit 2: CPUFANIN1 Input Control. 1: Pin119 (CPUFANIN1) acts as a FAN tachometer input. (Default) 0: Pin119 acts as a FAN control signal, and the output value is set by register bit 3. Bit 1: AUXFANIN1 output value, only if bit 0 is set to zero. Otherwise, this bit has no meaning. 1: Pin58(AUXFANIN1) generates a logic-high signal. 0: Pin58 generates a logic-low signal. (Default) Bit 0: AUXFANIN1 Input Control. Publication Release Date: Aug, 22, 2007 Version 1.4
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1: Pin58(AUXFANIN1) acts as a FAN tachometer input. (Default) 0, Pin58 acts as a FAN control signal, and the output value is set by bit 1.
8.38 Serial Bus Address Register - Index 48h (Bank 0)
Register Location: Power on Default Value: Attribute: Size:
7
48h 2Dh Read/Write 8 bits
6 5 4 3 2 1 0
Serial Bus Addr.
Reserved
Bit 7: Reserved (read only). Bit 6-0: Serial Bus address <7:1>
8.39 CPUFANOUT0/AUXFANOUT monitor Temperature source select register Index 49h (Bank 0)
Register Location: Power on Default Value: Attribute: Size:
7 6
49h 00h Read/Write 8 bits
5 4 3 2 1 0
CPUFANOUT0 TEMP_SEL[0] CPUFANOUT0 TEMP_SEL[1] CPUFANOUT0 TEMP_SEL[2] Reserved AUXFANOUT TEMP_SEL[0] AUXFANOUT TEMP_SEL[1] AUXFANOUT TEMP_SEL[2] Reserved
Bit 7: Reserved. Bit 6-4: AUXFANOUT Temperature Source Select 000: Select AUXTIN as AUXFANOUT monitor source. (Default) 001: Reserved. 010: Select PECI Agent 1 as AUXFANOUT monitor source. 011: Select PECI Agent 2 as AUXFANOUT monitor source. 100: Select PECI Agent 3 as AUXFANOUT monitor source.
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101: Select PECI Agent 4 as AUXFANOUT monitor source. Bit 3: Reserved. Bit 2-0: CPUFANOUT0 Temperature Source Select 000: Select CPUTIN as CPUFANOUT0 monitor source. (Default) 001: Reserved. 010: Select PECI Agent 1 as CPUFANOUT0 monitor source. 011: Select PECI Agent 2 as CPUFANOUT0 monitor source. 100: Select PECI Agent 3 as CPUFANOUT0 monitor source. 101: Select PECI Agent 4 as CPUFANOUT0 monitor source.
8.40 CPUFANOUT1 Monitor Temperature Source Select Register - Index 4Ah (Bank 0)
Register Location: Power on Default Value: Attribute: Size:
7 6
4Ah 00h Read/Write 8 bits
5 4 3 2 1 0
Reserved Reserved Reserved Reserved Reserved CPUFANOUT1 TEMP_SEL[0] CPUFANOUT1 TEMP_SEL[1] CPUFANOUT1 TEMP_SEL[2]
Bit 7-5: CPUFANOUT1 Temperature Source Select 000: Select SYSTIN as CPUFANOUT1 monitor source. (Default) 001: Select CPUTIN as CPUFANOUT1 monitor source. 010: Select AUXTIN as CPUFANOUT1 monitor source. 011: Reserved. 100: Select PECI Agent 1 as CPUFANOUT1 monitor source. 101: Select PECI Agent 2 as CPUFANOUT1 monitor source. 110: Select PECI Agent 3 as CPUFANOUT1 monitor source. 111: Select PECI Agent 4 as CPUFANOUT1 monitor source. Bit 4-0: Reserved.
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8.41 Fan Divisor Register II - Index 4Bh (Bank 0)
Register Location: Power on Default Value: Attribute: Size:
7 6
4Bh 44h Read/Write 8 bits
5 4 3 2 1 0
Reserved Reserved Reserved Reserved ADCOVSEL ADCOVSEL AUXFANIN0 DIV_B0 AUXFANIN0 DIV_B1
Bit 7-6: AUXFANIN0 Divisor bits1-0.
Note: Please see Bank0 Index 5Dh , Fan divisor table.
Bit 5-4: A/D Converter Clock Input select. 00: ADC clock select 22.5 KHz. (Default) 01: ADC clock select 5.6 KHz. (22.5K/4) 10: ADC clock select 1.4 KHz. (22.5K/16) 11: ADC clock select 0.35 KHz. (22.5K/64) Bit 3-2: Reserved. These two bits should be set to 01h, the default value. Bit 1-0: Reserved.
8.42 SMI#/OVT# Control Register - Index 4Ch (Bank 0)
Register Location: Power on Default Value: Attribute: Size:
7
4Ch 10h Read/Write 8 bits
6 5 4 3 2 1 0
Reserved Reserved OVTPOL DIS_OVT2 DIS_OVT3 EN_T1_ONE T2T3_INTMode CPUFANIN1 DIV_B2
Bit 7: CPUFANIN1 Divisor bit2. Bit 6: 1: SMI# output type of Temperature CPUTIN / AUXTIN is in Comparator Interrupt mode. Publication Release Date: Aug, 22, 2007 Version 1.4
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0: SMI# output type is in Two-Times Interrupt mode. (Default) Bit 5: 1: SMI# output type of temperature SYSTIN is One-Time Interrupt mode. 0: SMI# output type is Two-Times Interrupt mode. Bit 4: 1: Disable temperature sensor AUXTIN over-temperature (OVT) output. (Default) 0: Enable AUXTIN OVT output through pin OVT#. Bit 3: 1: Disable temperature sensor CPUTIN over-temperature (OVT) output. 0: Enable CPUTIN OVT output through pin OVT#. (Default) Bit 2: Over-temperature polarity. 1: OVT# active high. 0: OVT# active low. (Default) Bit 1-0: Reserved.
8.43 FAN IN/OUT Control Register - Index 4Dh (Bank 0)
Register Location: Power on Default Value: Attribute: Size: 4Dh 95h Read/Write 8 bits
7 6 5 4 3 2 1 0
FANINC1 FANOPV1 FANINC2 FANOPV2 FANINC3 FANOPV3 Reserved Reserved
Bit 7-6: Reserved. Bit 5: AUXFANIN0 output value, only if bit 4 is set to zero. 1: Pin111 (AUXFANIN0) generates a logic-high signal. 0: Pin111 generates a logic-low signal. (Default) Bit 4: AUXFANIN0 Input Control. 1: Pin111 (AUXFANIN0) acts as a FAN tachometer input. (Default) 0: Pin111 acts as a FAN control signal, and the output value is set by bit 5. Bit 3: CPUFANIN0 output value, only if bit 2 is set to zero. 1: Pin112 (CPUFANIN0) generates a logic-high signal. 0: Pin112 generates a logic-low signal. (Default) Bit 2: CPUFANIN0 Input Control. 1: Pin112 (CPUFANIN0) acts as a FAN tachometer input. (Default) 0: Pin112 acts as a FAN control signal, and the output value is set by bit 3. Publication Release Date: Aug, 22, 2007 Version 1.4
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Bit 1: SYSFANIN output value, only if bit 0 is set to zero. 1: Pin113 (SYSFANIN) generates a logic-high signal. 0: Pin113 generates a logic-low signal. (Default) Bit 0: SYSFANIN Input Control. 1: Pin113 (SYSFANIN) acts as a FAN tachometer input. (Default) 0: Pin113 acts as a FAN control signal, and the output value is set by bit 1.
8.44 Register 50h ~ 5Fh Bank Select Register - Index 4Eh (Bank 0)
Register Location: Power on Default Value: Attribute: Size:
7 6
4Eh 80h Read/Write 8 bits
5 4 3 2 1 0
BANKSEL0 BANKSEL1 BANKSEL2 Reserved EN_CPUFANIN1_BP EN_AUXFANIN1_BP Reserved HBACS
Bit 7: HBACS - High byte access. 1: Access Index 4Fh high-byte register. (Default) 0: Access Index 4Fh low-byte register. Bit 6: Reserved. This bit should be set to zero. Bit 5: BEEP output control for AUXFANIN1 if the monitored value exceeds the threshold value. 1: Enable BEEP output. 0: Disable BEEP output. (Default) Bit 4: BEEP output control for CPUFANIN1 if the monitored value exceeds the threshold value. 1: Enable BEEP output. 0: Disable BEEP output. (Default) Bit 3: Reserved. This bit should be set to zero. Bit 2-0: Bank Select for Index Ports 0x50h~0x5Fh. The three-bit binary value corresponds to the bank number. For example, "010" selects bank2.
8.45 Winbond Vendor ID Register - Index 4Fh (Bank 0)
Register Location: Power on Default Value: Attribute: Size: 4Fh <15:0> = 5CA3h Read Only 16 bits
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15
8
7
0
VIDH
VIDL
Bit 15-8: Vendor ID High-Byte, if Index 4Eh,bit 7 is 1. Default 5Ch. Bit 7-0: Vendor ID Low Byte, if Index 4Eh,bit 7 is 0. Default A3h.
8.46 Reserved Register - Index 50h ~ 55h (Bank 0) 8.47 BEEP Control Register 1 - Index 56h (Bank 0)
Register Location: Power on Default Value: Attribute: Size:
7
56h 00h Read/Write 8 bits
6 5 4 3 2 1 0
EN_CPUVCORE_BP EN_VIN0_BP EN_AVCC_BP EN_3VCC_BP EN_SYSTIN_BP EN_CPUTIN_BP EN_SYSFANIN_BP EN_CPUFANIN0_BP
Bit 7: BEEP output control for CPUFANIN0 if the monitored value exceeds the threshold value. 1: Enable BEEP output. 0: Disable BEEP output. (Default) Bit 6: BEEP output control for SYSFANIN if the monitored value exceeds the threshold value. 1: Enable BEEP output. 0: Disable BEEP output. (Default) Bit 5: BEEP output control for temperature CPUTIN if the monitored value exceeds the threshold value. 1: Enable BEEP output. 0: Disable BEEP output. (Default) Bit 4: BEEP output control for temperature SYSTIN if the monitored value exceeds the threshold value. 1: Enable BEEP output. 0: Disable BEEP output. (Default) Bit 3: BEEP output control for 3VCC if the monitored value exceeds the threshold value. 1: Enable BEEP output. 0: Disable BEEP output. (Default) Bit 2: BEEP output control for AVCC if the monitored value exceeds the threshold value.
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1: Enable BEEP output. 0: Disable BEEP output. (Default) Bit 1: BEEP output control for VIN0 if the monitored value exceeds the threshold value. 1: Enable BEEP output. 0: Disable BEEP output. (Default) Bit 0: BEEP output control for CPUVCORE if the monitored value exceeds the threshold value. 1: Enable BEEP output. 0: Disable BEEP output. (Default)
8.48 BEEP Control Register 2 - Index 57h (Bank 0)
Register Location: Power on Default Value: Attribute: Size:
7
57h 80h Read/Write 8 bits
6 5 4 3 2 1 0
EN_VIN1_BP EN_VIN2_BP EN_VIN3_B E PN_AUXFANIN0_BP EN_CASEOPEN_BP EN_AUXTIN_BP EN_VIN4_BP EN_GBP
Bit 7: Global BEEP Control. 1: Enable global BEEP output. (Default) 0: Disable all BEEP output. Bit 6: BEEP output control for VIN4 if the monitor value exceeds the limit value. 1: Enable BEEP output. 0: Disable BEEP output. (Default) Bit 5: BEEP output control for temperature AUXTIN if the monitored value exceeds the threshold value. 1: Enable BEEP output. 0: Disable BEEP output. (Default) Bit 4: BEEP output control for CASEOPEN if the case has been opened. 1: Enable BEEP output. 0: Disable BEEP output. (Default) Bit 3: BEEP output control for AUXFANIN0 if the monitored value exceeds the threshold value. 1: Enable BEEP output. 0: Disable BEEP output. (Default) Bit 2: BEEP output control for VIN3 if the monitored value exceeds the threshold value. 1: Enable BEEP output. 0: Disable BEEP output. (Default) Bit 1: BEEP output control for VIN2 if the monitored value exceeds the threshold value. 1: Enable BEEP output. Publication Release Date: Aug, 22, 2007 Version 1.4
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0: Disable BEEP output. (Default) Bit 0: BEEP output control for VIN1 if the monitored value exceeds the threshold value. 1: Enable BEEP output. 0: Disable BEEP output. (Default)
8.49 Chip ID - Index 58h (Bank 0)
Register Location: Power on Default Value: Attribute: Size:
7
58h C1h Read Only 8 bits
6 5 4 3 2 1 0
CHIPID
Bit 7-0: Winbond Chip ID number. Default C1h.
8.50 Diode Selection Register - Index 59h (Bank 0)
Register Location: Power on Default Value: Attribute: Size:
7
59h 70h Read/Write 8 bits
6 5 4 3 2 1 0 CPUFANIN1 DIV_B0 CPUFANIN1 DIV_B1 AUXFANIN1 DIV_B0 AUXFANIN1 DIV_B1 SELPIIV1 SELPIIV2 SELPIIV3 AUXFANIN1 DIV_B2
Bit 7: AUXFANIN1 Divisor, bit 2. (See VBAT Monitor Control Register - Index 5Dh (Bank 0)) Bit 6: Diode mode selection for temperature AUXTIN, if Index 5Dh, bit 3 is set to 1. 1: CPU-compatible thermal diode. 0: Reserved. Bit 5: Diode mode selection for temperature CPUTIN, if Index 5Dh, bit2 is set to 1. 1: CPU-compatible thermal diode. 0: Reserved.
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Bit 4: Diode mode selection for temperature SYSTIN, if Index 5Dh, bit1 is set to 1. 1: CPU-compatible thermal diode. 0: Reserved. Bit 3-2: AUXFANIN1 Divisor, bits 1-0. (See VBAT Monitor Control Register - Index 5Dh (Bank 0)) Bit 1-0: CPUFANIN1 Divisor, bits 1-0. (See VBAT Monitor Control Register - Index 5Dh (Bank 0))
8.51 Reserved Register - Index 5Ah ~ 5Ch (Bank 0) 8.52 VBAT Monitor Control Register - Index 5Dh (Bank 0)
Register Location: Power on Default Value: Attribute: Size: 5Dh 04h Read/Write 8 bits
7 6 5 4 3 2 1 0
EN_VBAT_MNT DIODES1 DIODES2 DIODES3 Reserved SYSFANIN DIV_B2 CPUFANIN0 DIV_B2 AUXFANIN0 DIV_B2
Bit 7: AUXFANIN0 Divisor, bit 2. Bit 6: CPUFANIN0 Divisor, bit 2. Bit 5: SYSFANIN Divisor, bit 2. Fan divisor table:
BIT 2 BIT 1 BIT 0 FAN DIVISOR BIT 2 BIT 1 BIT 0 FAN DIVISOR
0 0 0 0
0 0 1 1
0 1 0 1
1 2 4 8
1 1 1 1
0 0 1 1
0 1 0 1
16 32 64 128
Bit 4: Reserved. Bit 3: Sensor type selection for AUXTIN. 1: Diode sensor. 0: Thermistor sensor. Bit 2: Sensor type selection for CPUTIN. 1: Diode sensor. 0: Thermistor sensor. Bit 1: Sensor type selection for SYSTIN. 1: Diode sensor. 0: Thermistor sensor.
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Bit 0: 1: Enable battery voltage monitor. When this bit changes from zero to one, it takes one monitor cycle time to update the VBAT reading value register. 0: Disable battery voltage monitor.
8.53 Critical Temperature and Current Mode Enable Register - Index 5Eh (Bank 0)
Register Location: Power on Default Value: Attribute: Size:
7 6 5
5Eh 04h Read/Write 8 bits
4 3 2 1 0
Reserved EN_SYSTIN Current Mode EN_CPUTIN Current Mode EN_AUXTIN Current Mode EN_SYSFANOUT Critical TEMP EN_CPUFANOUT Critical TEMP EN_AUXFANOUT Critical TEMP EN_CPUFANOUT1 Critical TEMP
Bit 7: 1: Enable CPUFANOUT1 critical temperature protection. 0: Disable CPUFANOUT1 critical temperature protection. (Default) Bit 6: 1: Enable AUXFANOUT critical temperature protection. 0: Disable AUXFANOUT critical temperature protection. (Default) Bit 5: 1: Enable CPUFANOUT0 critical temperature protection. 0: Disable CPUFANOUT0 critical temperature protection. (Default) Bit 4: 1: Enable SYSFANOUT critical temperature protection. 0: Disable SYSFANOUT critical temperature protection. (Default) Bit 3: Enable AUXTIN Current Mode. 1: Temperature sensing of AUXTIN by Current Mode. 0: Temperature sensing of AUXTIN depends on the setting of Index 5Dh and 59h. (Default) Bit 2: Enable CPUTIN Current Mode. 1: Temperature sensing of CPUTIN by Current Mode. (Default) 0: Temperature sensing of CPUTIN depends on the setting of Index 5Dh and 59h. Bit 1: Enable SYSTIN Current Mode. 1: Temperature sensing of SYSTIN by Current Mode. 0: Temperature sensing of SYSTIN depends on the setting of Index 5Dh and 59h. (Default) Bit 0: Reserved.
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8.54 Reserved Register - Index 5Fh (Bank 0) 8.55 CPUFANOUT1 PWM Output Frequency Configuration Register - Index 60h (Bank 0)
Register Location: Power on Default Value: Attribute: Size:
7
60h 04h Read/Write 8 bits
6 5 4 3 2 1 0
PWM_SCALE4
PWM_CLK_SEL4
The register is only meaningful when CPUFANOUT1 is programmed for PWM output.
Bit 7: CPUFANOUT1 PWM Input Clock Source Select. This bit selects the clock source for PWM output. 0: clock source is 24 MHz. 1: clock source is 180 KHz. Bit 6-0: CPUFANOUT1 PWM Pre-Scale divider. The clock source of PWM output is divided by this seven-bit value to calculate the actual PWM output frequency. PWM output frequency =
Input Clock 1 Pre_Scale Divider 256
The maximum value of the divider is 127 (7Fh), and it should not be set to 0.
8.56 CPUFANOUT1 Output Value Select Register - Index 61h (Bank 0)
Register Location: Power on Default Value: Attribute: Size:
7 6
61h Strap by FAN_SET2(Pin 83) Read/Write 8 bits
5 4 3 2 1 0
CPUFANOUT1 Value
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(1)If CPUFANOUT1 is programmed for PWM output (Bank0 Index 62h, bit 6 is 0) Bit 7-0: CPUFANOUT1 PWM Duty Cycle.The PWM duty cycle is equal to this eight-bit value, divided by 255, times 100%. FFh creates a duty cycle of 100%, and 00h creates a duty cycle of 0%. (2)If CPUFANOUT1 is programmed for DC output (Bank0 Index 62h, bit 6 is 1) Bit 7-2: CPUFANOUT1 voltage control.The output voltage is calculated according to this equation. OUTPUT Voltage = Bit 1-0: Reserved.
AVCC *
FANOUT 64
8.57 FAN Configuration Register III - Index 62h (Bank 0)
Register Location: Power on Default Value: Attribute: Size:
7 6 5 4
62h 40h Read/Write 8 bits
3 2 1 0
Target Temperature Tolerance / CPUFANIN1 Target Speed Tolerance CPUFANOUT1_Mode CPUFANOUT1_Mode CPUFANOUT1_SEL Reserved
Bit 7: Reserved. Bit 6: CPUFANOUT1 output mode selection. 0: CPUFANOUT1 pin produces a PWM output duty cycle. 1: CPUFANOUT1 pin produces DC output. (Default) Bit 5-4: CPUFANOUT1 mode control. Set 00, CPUFANOUT1 is in Manual Mode. (Default) Set 01, CPUFANOUT1 is in Thermal CruiseTM Mode. Set 10, CPUFANOUT1 is in Fan Speed CruiseTM Mode. Set 11, CPUFANOUT1 is in SMART FANTM III Mode. (1)In Thermal CruiseTM mode or SMART FANTM III mode: Bit3-0: Tolerance of select temperature source Target Temperature. (2)In Fan Speed CruiseTM mode: Bit3-0: Tolerance of CPUFANIN1 Target Speed.
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8.58 Target Temperature Register/CPUFANIN1 Target Speed Register - Index 63h (Bank 0)
Register Location: Power on Default Value: Attribute: Size:
7 6 5
63h 00h Read/Write 8 bits
4 3 2 1 0
Target Temperature / Target Speed
(1)In Thermal CruiseTM mode or SMART FANTM III mode: Bit 7: Reserved. Bit 6-0: Target Temperature of select temperature source. (2)In Fan Speed CruiseTM mode: Bit 7-0: CPUFANIN1 Target Speed.
8.59 CPUFANOUT1 Stop Value Register - Index 64h (Bank 0)
Register Location: Power on Default Value: Attribute: Size:
7 6
64h 01h Read/Write 8 bits
5 4 3 2 1 0
CPUFANOUT1 Stop Value
In Thermal CruiseTM mode, the CPUFANOUT1 value decreases to this eight-bit value if the temperature stays below the lowest temperature limit. This value should not be zero. Please note that Stop Value does not mean that the fan really stops. It means that if the temperature keeps below low temperature limit, then the fan speed keeps on decreasing until reaching a minimum value, and this is Stop Value.
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8.60 CPUFANOUT1 Start-up Value Register - Index 65h (Bank 0)
Register Location: Power on Default Value: Attribute: Size:
7 6
65h 01h Read/Write 8 bits
5 4 3 2 1 0
CPUFANOUT1 Start-up Value
In Thermal CruiseTM mode, CPUFANOUT1 value increases from zero to this eight-bit register value to provide a minimum value to turn on the fan.
8.61 CPUFANOUT1 Stop Time Register - Index 66h (Bank 0)
Register Location: Power on Default Value: Attribute: Size:
7 6
66h 3Ch Read/Write 8 bits
5 4 3 2 1 0
CPUFANOUT1 Stop Time
In Thermal CruiseTM mode or SMART FANTM III mode, if the stop value is enabled, this register determines the amount of time it takes the CPUFANOUT1 value to fall from the stop value to zero. (1)For PWM output: The units are intervals of 0.1 second. The default time is 6 seconds. (2)For DC output: The units are intervals of 0.4 second. The default time is 24 seconds.
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8.62 CPUFANOUT0 Maximum Output Value Register - Index 67h (Bank 0)
Register Location: Power on Default Value: Attribute: Size:
7 6
67h FFh Read/Write 8 bits
5 4 3 2 1 0
CPUFANOUT0 Max. Value
In SMART FANTM III mode, the CPUFANOUT0 value increases to this value. This value cannot be zero, and it cannot be lower than the CPUFANOUT0 Stop value.
8.63 CPUFANOUT0 Output Step Value Register - Index 68h (Bank 0)
Register Location: Power on Default Value: Attribute: Size: 68h 01h Read/Write 8 bits
7 6 5 4 3 2 1 0
CPUFANOUT0 Step
In SMART FANTM III mode, the CPUFANOUT0 value decreases or increases by this eight-bit value, when needed.
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8.64 CPUFANOUT1 Maximum Output Value Register - Index 69h (Bank 0)
Register Location: Power on Default Value: Attribute: Size:
7 6
69h FFh Read/Write 8 bits
5 4 3 2 1 0
CPUFANOUT1 Max. Value
In SMART FANTM III mode, the CPUFANOUT1 value increases to this value. This value cannot be zero, and it cannot be lower than the CPUFANOUT1 Stop value.
8.65 CPUFANOUT1 Output Step Value Register - Index 6Ah (Bank 0)
Register Location: Power on Default Value: Attribute: Size:
7
6Ah 01h Read/Write 8 bits
6 5 4 3 2 1 0
CPUFANOUT1 Step
In SMART FANTM III mode, the CPUFANOUT1 value decreases or increases by this eight-bit value, when needed.
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8.66 SYSFANOUT Critical Temperature register - Index 6Bh (Bank 0)
Register Location: Power on Default Value: Attribute: Size: 6Bh FFh Read/Write 8 bits
7
6
5
4
3
2
1
0
SYSFANOUT Threshold temperature
In Thermal CruiseTM mode, when the function of SYSFANOUT temperature sensing is enabled, and the monitored temperature exceeds the threshold temperature, the SYSFANOUT will work at full speed.
8.67 CPUFANOUT0 Critical Temperature Register - Index 6Ch (Bank 0)
Register Location: Power on Default Value: Attribute: Size:
7 6
6Ch FFh Read/Write 8 bits
5 4 3 2 1 0
CPUFANOUT0 Critical temperature
In Thermal CruiseTM mode, when the function of CPUFANOUT0 temperature sensing is enabled, and the monitored temperature exceeds the threshold temperature, the CPUFANOUT0 will work at full speed.
8.68 AUXFANOUT Critical Temperature Register - Index 6Dh (Bank 0)
Register Location: Power on Default Value: Attribute: Size: 6Dh FFh Read/Write 8 bits
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7
6
5
4
3
2
1
0
AUXFANOUT Critical temperature
In Thermal CruiseTM mode, when the function of AUXFANOUT temperature sensing is enabled, and the monitored temperature exceeds the threshold temperature, the AUXFANOUT will work at full speed.
8.69 CPUFANOUT1 Critical Temperature Register - Index 6Eh (Bank 0)
Register Location: Power on Default Value: Attribute: Size: 6Eh FFh Read/Write 8 bits
7
6
5
4
3
2
1
0
CPUFANOUT1 Critical temperature
In Thermal CruiseTM mode, when the function of CPUFANOUT1 temperature sensing is enabled, and the monitored temperature exceeds the threshold temperature, the CPUFANOUT1 will work at full speed.
8.70 CPUTIN Temperature Sensor Temperature (High Byte) Register - Index 50h (Bank 1)
Register Location: Attribute: Size: 50h Read Only 8 bits
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7
6
5
4
3
2
1
0
TEMP<8:1>
Bit 7-0: Temperature <8:1> of the CPUTIN sensor, The nine-bit value is in units of 0.5C.
8.71 CPUTIN Temperature Sensor Temperature (Low Byte) Register - Index 51h (Bank 1)
Register Location: Attribute: Size: 51h Read Only 8 bits
7 6 5 4 3 2 1 0
Reserved
TEMP<0>
Bit 7: Temperature <0> of the CPUTIN sensor, The nine-bit value is in units of 0.5C. Bit 6-0: Reserved.
8.72 CPUTIN Temperature Sensor Configuration Register - Index 52h (Bank 1)
Register Location: Power on Default Value: Attribute: Size: 52h 00h Read/Write 8 bits
7 6 5 4 3 2 1 0
STOP OVTMOD Reserved FAULT FAULT Reserved Reserved Reserved
Bit 7-5: Reserved. This bit should be set to zero. Bit 4-3: Number of faults to detect before setting OVT# output. This avoids false tripping due to noise.
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Bit 2: Reserved. This bit should be set to zero. Bit 1OVT# mode select. 0: Compared mode. (Default) 1: Interrupt mode. Bit 00: Monitor CPUTIN. 1: Stop monitoring CPUTIN.
8.73 CPUTIN Temperature Sensor Hysteresis (High Byte) Register - Index 53h (Bank 1)
Register Location: Power on Default Value: Attribute: Size:
7
53h 4Bh Read/Write 8 bits
6 5 4 3 2 1 0
THYST<8:1>
Bit 7-0: Hysteresis temperature bits 8-1.The nine-bit value is in units of 0.5C, and the default is 75C.
8.74 CPUTIN Temperature Sensor Hysteresis (Low Byte) Register - Index 54h (Bank 1)
Register Location: Power on Default Value: Attribute: Size: 54h 00h Read/Write 8 bits
7 6 5 4 3 2 1 0
Reserved
THYST<0>
Bit 7: Hysteresis temperature bit 0. The nine-bit value is in units of 0.5C. Bit 6-0: Reserved.
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8.75 CPUTIN Temperature Sensor Over-temperature (High Byte) Register - Index 55h (Bank1)
Register Location: Power on Default Value: Attribute: Size:
7
55h 50h Read/Write 8 bits
6 5 4 3 2 1 0
TOVF<8:1>
Bit 7-0: Over-temperature bits 8-1.The nine-bit value is in units of 0.5C, and the default is 80C.
8.76 CPUTIN Temperature Sensor Over-temperature (Low Byte) Register - Index 56h (Bank 1)
Register Location: Power on Default Value: Attribute: Size:
7
56h 00h Read/Write 8 bits
6 5 4 3 2 1 0
Reserved
TOVF<0>
Bit 7: Over-temperature bit 0. The nine-bit value is in units of 0.5C. Bit 6-0: Reserved.
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8.77 AUXTIN Temperature Sensor Temperature (High Byte) Register - Index 50h (Bank 2)
Register Location: Attribute: Size: 50h Read Only 8 bits
7 6 5 4 3 2 1 0
TEMP<8:1>
Bit 7: Temperature <8:1> of the AUXTIN sensor. The nine-bit value is in units of 0.5C.
8.78 AUXTIN Temperature Sensor Temperature (Low Byte) Register - Index 51h (Bank 2)
Register Location: Attribute: Size: 51h Read Only 8 bits
7 6 5 4 3 2 1 0
Reserved
TEMP<0>
Bit 7: Temperature <0> of the AUXTIN sensor. The nine-bit value is in units of 0.5C. Bit 6-0: Reserved.
8.79 AUXTIN Temperature Sensor Configuration Register - Index 52h (Bank 2)
Register Location: Power on Default Value: Attribute: Size: 52h 00h Read/Write 8 bits
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7
6
5
4
3
2
1
0
STOP OVTMOD Reserved FAULT FAULT Reserved Reserved Reserved
Bit 7-5: Reserved. This bit should be set to zero. Bit 4-3: Number of faults to detect before setting OVT# output. This avoids false tripping due to noise. Bit 2: Reserved. This bit should be set to zero. Bit 1: OVT# mode select. 0: Compared mode. (Default) 1: Interrupt mode. Bit 00: Monitor AUXTIN. 1: Stop monitoring AUXTIN.
8.80 AUXTIN Temperature Sensor Hysteresis (High Byte) Register - Index 53h (Bank 2)
Register Location: Power on Default Value: Attribute: Size: 53h 4Bh Read/Write 8 bits
7 6 5 4 3 2 1 0
THYST<8:1>
Bit 7-0: Hysteresis temperature, bits 8-1. The nine-bit value is in units of 0.5C, and the default is 75C.
8.81 AUXTIN Temperature Sensor Hysteresis (Low Byte) Register - Index 54h (Bank 2)
Register Location: Power on Default Value: Attribute: Size: 54h 00h Read/Write 8 bits
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7
6
5
4
3
2
1
0
Reserved
THYST<0>
Bit 7: Hysteresis temperature, bit 0. The nine-bit value is in units of 0.5C. Bit 6-0: Reserved.
8.82 AUXTIN Temperature Sensor Over-temperature (High Byte) Register - Index 55h (Bank 2)
Register Location: Power on Default Value: Attribute: Size: 55h 50h Read/Write 8 bits
7 6 5 4 3 2 1 0
TOVF<8:1>
Bit 7-0: Over-temperature, bits 8-1. The nine-bit value is in units of 0.5C, and the default is 80C.
8.83 AUXTIN Temperature Sensor Over-temperature (Low Byte) Register - Index 56h (Bank 2)
Register Location: Power on Default Value: Attribute: Size: 56h 00h Read/Write 8 bits
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7
6
5
4
3
2
1
0
Reserved
TOVF<0>
Bit 7: Over-temperature, bit 0. The nine-bit value is in units of 0.5C. Bit 6-0: Reserved.
8.84 Interrupt Status Register 3 - Index 50h (Bank 4)
Register Location: Power on Default Value: Attribute: Size:
7
50h 00h Read Only 8 bits
6 5 4 3 2 1 0 3VSB VBAT TAR3 Reserved CPUFANIN1 AUXFANIN1 Reserved Reserved
Bit 7-6: Reserved. Bit 5: A one indicates the fan count limit of AUXFANIN1 has been exceeded. Bit 4: A one indicates the fan count limit of CPUFANIN1 has been exceeded. Bit 3: Reserved Bit 2: A one indicates that the AUXTIN temperature has been over the target temperature for three minutes at full fan speed in Thermal CruiseTM mode. Bit 1: A one indicates the high or low limit of VBAT has been exceeded. Bit 0: A one indicates the high or low limit of 3VSB has been exceeded.
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8.85 SMI# Mask Register 4 - Index 51h (Bank 4)
Register Location: Power on Default Value: Attribute: Size: 51h 13h Read/Write 8 bits
7 6 5 4 3 2 1 0 3VSB VBAT Reserved Reserved TAR3 Reserved Reserved Reserved
Bit 7-5: Reserved. Bit 4: A one disables the corresponding interrupt status bit for the SMI interrupt. (See Interrupt Status Register 3 - Index 50h (Bank 4)) Bit 3-2: Reserved. Bit 1-0: A one disables the corresponding interrupt status bit for the SMI interrupt. (See Interrupt Status Register 3 - Index 50h (Bank 4))
8.86 Reserved Register - Index 52h (Bank 4) 8.87 BEEP Control Register 3 - Index 53h (Bank 4)
Register Location: Power on Default Value: Attribute: Size:
7
53h 00h Read/Write 8 bits
6 5 4 3 2 1 0 EN_3VSB_BP EN_VBAT_BP Reserved Reserved Reserved EN_USER_BP Reserved Reserved
Bit 7-6: Reserved. Bit 5: User-defined BEEP output function. 0: Make BEEP inactive. (Default) 1: Make BEEP active. Bit 4-2: Reserved.
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Bit 1: BEEP output control for VBAT if the monitored value exceeds the threshold value. 1: Enable BEEP output. 0: Disable BEEP output. (Default) Bit 0: BEEP output control for 3VSB if the monitored value exceeds the threshold value. 1: Enable BEEP output. 0: Disable BEEP output. (Default)
8.88 SYSTIN Temperature Sensor Offset Register - Index 54h (Bank 4)
Register Location: Power on Default Value: Attribute: Size:
7 6
54h 00h Read/Write 8 bits
5 4 3 2 1 0
OFFSET<7:0>
Bit 7-0: SYSTIN temperature offset value. The value in this register is added to the monitored value so that the read value will be the sum of the monitored value and this offset value.
8.89 CPUTIN Temperature Sensor Offset Register - Index 55h (Bank 4)
Register Location: Power on Default Value: Attribute: Size:
7 6
55h 00h Read/Write 8 bits
5 4 3 2 1 0
OFFSET<7:0>
Bit 7-0: CPUTIN temperature offset value. The value in this register will be added to the monitored value so that the read value is the sum of the monitored value and this offset value.
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8.90 AUXTIN Temperature Sensor Offset Register - Index 56h (Bank 4)
Register Location: Power on Default Value: Attribute: Size:
7
56h 00h Read/Write 8 bits
6 5 4 3 2 1 0
OFFSET<7:0>
Bit 7-0: AUXTIN temperature offset value. The value in this register is added to the monitored value so that the reading value is the sum of the monitored value and this offset value.
8.91 Reserved Register - Index 57h-58h (Bank 4) 8.92 Real Time Hardware Status Register I - Index 59h (Bank 4)
Register Location: Power on Default Value: Attribute: Size:
7
59h 00h Read Only 8 bits
6 5 4 3 2 1 0 CPUVCORE_STS VIN0_STS AVCC_STS 3VCC_STS SYSTIN_STS CPUTIN_STS SYSFANIN_STS CPUFANIN0_STS
Bit 7: CPUFANIN0 status. 1: Fan speed count is over the threshold value. 0: Fan speed count is in the allowed range. Bit 6: SYSFANIN status. 1: Fan speed count is over the threshold value. 0: Fan speed count is in the allowed range. Bit 5: CPUTIN temperature sensor status. 1: Temperature exceeds the over-temperature value. 0: Temperature is under the hysteresis value. Publication Release Date: Aug, 22, 2007 Version 1.4
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Bit 4: SYSTIN temperature sensor status. 1: Temperature exceeds the over-temperature value. 0: Temperature is under the hysteresis value. Bit 3: 3VCC Voltage status. 1: 3VCC voltage is over or under the allowed range. 0: 3VCC voltage is in the allowed range. Bit 2: AVCC Voltage status. 1: AVCC voltage is over or under the allowed range. 0: AVCC voltage is in the allowed range. Bit 1: VIN0 Voltage status. 1: VIN0 voltage is over or under the allowed range. 0: VIN0 voltage is in the allowed range. Bit 0: CPUVCORE Voltage status. 1: CPUVCORE voltage is over or under the allowed range. 0: CPUVCORE voltage is in the allowed range.
8.93 Real Time Hardware Status Register II - Index 5Ah (Bank 4)
Register Location: Power on Default Value: Attribute: Size:
7
5Ah 00h Read Only 8 bits
6 5 4 3 2 1 0 VIN1_STS TAR4_STS CPUFANIN1_STS AUXFANIN0_STS CASEOPEN_STS AUXTIN_STS TAR1_STS TAR2_STS
Bit 7: Smart Fan of CPUFANIN0 warning status. 1: Selected temperature has been over the target temperature for three minutes at full fan speed in Thermal CruiseTM mode. 0: Selected temperature has not reached the warning range. Bit 6: Smart Fan of SYSFANIN warning status. 1: SYSTIN temperature has been over the target temperature for three minutes at full fan speed in Thermal CruiseTM mode. 0: SYSTIN temperature has not reached the warning range. Bit 5: AUXTIN temperature sensor status. 1: Temperature exceeds the over-temperature value. 0: Temperature is under the hysteresis value.
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Bit 4: Case Open status. 1: Case-open is detected and latched. 0: Case-open is not latched. Bit 3: AUXFANIN0 status. 1: Fan speed count is over the threshold value. 0: Fan speed count is in the allowed range. Bit 2: CPUFANIN1 status. 1: Fan speed count is over the threshold value. 0: Fan speed count is in the allowed range. Bit 1: Smart Fan of CPUFANIN1 warning status. 1: Selected temperature has been over the target temperature for three minutes at full fan speed in Thermal CruiseTM mode. 0: Selected temperature has not reached the warning range. Bit 0: VIN1 Voltage status. 1: VIN1 voltage is over or under the allowed range. 0: VIN1 voltage is in the allowed range.
8.94 Real Time Hardware Status Register III - Index 5Bh (Bank 4)
Register Location: Power on Default Value: Attribute: Size: 5Bh 00h Read Only 8 bits
7 6 5 4 3 2 1 0 VSB_STS VBAT_STS TAR3_STS Reserved VIN3_STS VIN2_STS Reserved AUXFANIN1_STS
Bit 7: AUXFANIN1 status. 1: Fan speed count is over the threshold value. 0: Fan speed count is in the allowed range. Bit 6: Reserved. Bit 5: VIN2 Voltage status. 1: VIN2 voltage is over or under the allowed range. 0: VIN2 voltage is in the allowed range. Bit 4: VIN3 Voltage status. 1: VIN3 voltage is over or under the allowed range. 0: VIN3 voltage is in the allowed range. Bit 3: Reserved Publication Release Date: Aug, 22, 2007 Version 1.4
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Bit 2: Smart Fan of AUXFANIN warning status. 1: Selected temperature has been over the target temperature for three minutes at full fan speed in Thermal CruiseTM mode. 0: Selected temperature has not reached the warning range. Bit 1: VBAT Voltage status. 1: VBAT voltage is over or under the allowed range. 0: VBAT voltage is in the allowed range. Bit 0: 3VSB Voltage status. 1: 3VSB voltage is over or under the allowed range. 0: 3VSB voltage is in the allowed range.
8.95 Reserved Register - Index 5Ch ~ 5Fh (Bank 4) 8.96 Value RAM 2 Index 50h-59h (Bank 5)
ADDRESS A6-A0 DESCRIPTION
50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch
3VSB reading VBAT reading. The reading is meaningless unless EN_VBAT_MN (Bank0 Index 5Dh, bit0) is set. Reserved AUXFANIN1 reading Note: This location stores the number of counts of the internal clock per revolution. 3VSB High Limit 3VSB Low Limit VBAT High Limit VBAT Low Limit Reserved Reserved Reserved Reserved AUXFANIN1 Fan Count Limit Note: It is the number of counts of the internal clock for the Low Limit of the fan speed.
8.97 Reserved Register - Index 50h ~ 57h (Bank 6)
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9. SERIAL PERIPHERAL INTERFACE
The W83627DHG provides a bridge of the Low Pin Count (LPC) Interface to Serial Peripheral Interface (SPI). The signals in the SPI are transmitted through Pin 2 (SCK), Pin 19 (SCE#), Pin 58 (SI), and Pin 118 (SO). In the Super I/O (W83627DHG), these 4 pins are multi-functional. The SPI functions are activated through strapping. Pin 52 determines whether to enable or disable the SPI functions. In the Super I/O (W83627DHG), the SPI functions are activated when Pin 52 is pulled-up to the power source. The function status can be seen/read at CR[24h], bit 1. The SPI is primarily used to store the BIOS ROM. When booting the computer, the memory read instructions or timing sequences are transmitted from the CPU, the South Bridge, the LPC bus to the Super I/O (W83627DHG). After receiving the instruction, the Super I/O (W83627DHG) generates and transmits the correct instructions and memory addresses to the SPI which responds with the corresponding data of the addresses. The data are placed to the LPC bus by the Super I/O (W83627DHG) and returned to the South Bridge. All of the data are read in this manner. By setting the registers shown at Table 9.3, the Super I/O (W83627DHG) supports all the instructions given, such as erase, read, program, to SPI flash. For more details, please see Table 9.2. To make it more user-friendly, regularly used SPI instructions/functions can be generated via the LPC I/O read/write commands. That is, the flash devices with SPI can be programmed, erased, or read on the motherboard.
9.1
Using the SPI Interface via the LPC
The allowed range is 8 bytes above the base address. The base address is configured at Configuration Register CR62h and CR63h in Logical Device 6. For example, if 03h is written to Configuration Register CR62h, and F8h to Configuration Register CR63h, 03F8h ~ 03FFh is the allowed range. Table 9.1 Base Address Setting
LOGICAL DEVICE
CONFIGURATION REGISTER
BIT
FUNCTION
6
62 63
7:0 7:0
High byte of Base Address Low byte of Base Address
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Functions and Definitions The functions and definitions of the 8 bytes are shown in the following table. Table 9.2 SPI Address Map
ADDRESS BIT FUNCTION DESCRIPTION
Base+0 Base+1 Base+2 Base+3 Base+4 Base+5 Base+6 Base+7
7:0 7:4 3:0 7:0 7:0 7:0 7:0 7:0 7:0
CMD MODE ADD2 ADD1 ADD0 DATA0 DATA1 DATA2 DATA3
Commands or instructions of each SPI device Mode execution. Please see the Table 9.3 for the details of each mode. Address [19:16] Address [15:8] Address [7:0] Data byte 0 Data byte 1 Data byte 2 Data byte 3
Usages Write SPI instructions to Base+0. Set up the addresses and the data in Base+2 ~ Base+7. Implement the instruction by setting the instruction mode in Base+1. Accessing SPI Devices Take erasing the SPI for example, first write the "Chip Erase" instruction to Base+0 and 1Xh1 to Base+1 (Bit3~Bit0 of Base +1 is the parameter of address[19:16].). The instruction modes are listed in the table below. For Mode 1, only a one-byte instruction is generated. For Mode 2, in addition to a one-byte instruction, a one-byte parameter, which is set up in Base+4 in advance, is also generated. The "X" of 1X stands for the parameters of the address[19:16] (A19~A16, the most significant byte (MSB) of the address).
1
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Table 9.3 MODE
MODE DEFINITION FUNCTION COMMAND EXAMPLE
1 2 3 4 5 6 7 8 9 a b
CMD CMD_Da(1) CMD_Da(2) CMD_Add(3) CMD_Ad(3)_Da(1)_W CMD_Ad(3)_Da(4)_W CMD_Ad(4)_Da(4)_R CMD_Ad(3)_Da(1)_R CMD_Ad(3)_Da(2)_R CMD_Ad(3)_Da(3)_R CMD_Ad(3)_Da(4)_R
Command only Command with 1byte data write Command with 2bytes data read Command with 3 bytes address Command with 3bytes address and 1byte data read Command with 3bytes address and 4bytes data write Command with 3bytes and a dummy byte address and 4byte data read Command with 3bytes address and 1byte data read Command with 3bytes address and 2bytes data read Command with 3bytes address and 3bytes data read Command with 3bytes address and 4 bytes data read
Chip Enable, Write Enable, Write Disable Write Status Register Read ID (Atmel(R))
Block Erase, Sector Erase
Byte Program (1 byte) Page Program (4 bytes) FAST READ (4 bytes) READ, Read Status Read ID (ST/SST(R)) Read ID (Winbond (R)) Read ID (PMC(R))
Reading Data From SPI Devices First, write the "Read" instruction to Base+0. Then write the addresses to Base+2 ~ Base+3. Last, write 8X to Base+1. Programming SPI Devices First, write the "Byte Program" instruction to Base+0. Then write the addresses into Base+2 ~ Base+3 and parameters to Base+4. Last, write 5X to Base+1. For correct programming, make sure the state of the device is ready and write enabled. * For more details, please see the Programming Guide of the W83627DHG.
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10. FLOPPY DISK CONTROLLER 10.1 FDC Functional Description
The floppy disk controller (FDC) of the W83627DHG integrates all of the logic required for floppy disk control. The FDC implements a FIFO which provides better system performance in multi-master systems, and the digital data separator supports data rates up to 2 M bits/sec. The FDC includes the following blocks: Precompensation, Data Rate Selection, Digital Data Separator, FIFO, and FDC Core. The rest of this section discusses these blocks through the following topics: FIFO, Data Separator, Write Precompensation, Perpendicular Recording mode, FDC core, FDC commands, and FDC registers.
10.1.1 FIFO (Data)
The FIFO is 16 bytes in size and has programmable threshold values. All command parameter information and disk data transfers go through the FIFO. Data transfers are governed by the RQM (Request for Master) and DIO (Data Input/Output) bits in the Main Status Register. The FIFO is defaulted to disabled mode after any form of reset, which maintains PC/AT hardware compatibility. The default values can be changed through the configure command. The advantage of the FIFO is that it lets the system have a larger DMA latency without causing disk errors. The following tables give several examples of the delays with the FIFO. The data are based upon the following formula: DELAY = THRESHOLD # x (1 / DATA RATE) * 8 - 1.5 s
FIFO THRESHOLD MAXIMUM DELAY UNTIL SERVICING AT 500K BPS
1 Byte 2 Byte 8 Byte 15 Byte
FIFO THRESHOLD
Data Rate 1 x 16s - 1.5 s = 14.5 s 2 x 16 s - 1.5 s = 30.5 s 8 x 16 s - 1.5 s = 6.5 s 15 x 16 s - 1.5 s = 238.5 s
MAXIMUM DELAY UNTIL SERVICING AT 1M BPS
1 Byte 2 Byte 8 Byte 15 Byte
Data Rate 1 x 8 s - 1.5 s = 6.5 s 2 x 8 s - 1.5 s = 14.5 s 8 x 8 s - 1.5 s = 62.5 s 15 x 8 s - 1.5 s = 118.5 s
At the start of a command, the FIFO is always disabled, and command parameters must be sent based upon the RQM and DIO bit settings in the Main Status Register. When the FDC enters the command execution phase, it clears the FIFO off any data to ensure that invalid data are not transferred. An overrun or underrun terminates the current command and data transfer. Disk writes complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to remove the remaining data so that the result phase may be entered. DMA transfers are enabled by the specify command and are initiated by the FDC when the LDRQ pin is activated during a data transfer command.
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10.1.2 Data Separator
The function of the data separator is to lock onto incoming serial read data. When a lock is achieved, the serial front-end logic in the chip is provided with a clock that is synchronized with the read data. The synchronized clock, called the Data Window, is used to internally sample the serial data portion of the bit cell, and the alternate state samples the clock portion. Serial-to-parallel conversion logic separates the read data into clock and data bytes. The Digital Data Separator (DDS) has three parts: control logic, error adjustment, and speed tracking. The control logic generates RDD and RWD for every pulse input, and any data pulse input is synchronized and then adjusted immediately by error adjustment. A digital integrator keeps track of the speed changes in the input data stream.
10.1.3 Write Precompensation
The write precompensation logic minimizes bit shifts in the RDDATA stream from the disk drive. Shifting of bits is a known phenomenon in magnetic media and depends on the disk media and the floppy drive. The FDC monitors the bit stream that is being sent to the drive. The data patterns that require precompensation are well known, so, depending on the pattern, the bit is shifted either early or late, relative to the surrounding bits.
10.1.4 Perpendicular Recording Mode
The FDC is also capable of interfacing directly to perpendicular recording floppy drives. Perpendicular recording differs from the traditional longitudinal method in that the magnetic bits are oriented vertically. This scheme packs more data bits into the same area. FDCs with perpendicular recording drives can read standard 3.5" floppy disks and can read and write perpendicular media. Some manufacturers offer drives that can read and write standard and perpendicular media in a perpendicular media drive. A single command puts the FDC into perpendicular mode. All other commands operate as they normally do. Perpendicular mode requires a 1 Mbps data rate for the FDC, and, at this data rate, the FIFO manages the host interface bottleneck due to the high speed of data transfer to and from the disk.
10.1.5 FDC Core
The W83627DHG FDC is capable of performing twenty commands. Each command is initiated by a multi-byte transfer from the microprocessor, and the result may be a multi-byte transfer back to the microprocessor. Each command consists of three phases: command, execution, and result. Command The microprocessor issues all required information to the controller to perform a specific operation. Execution The controller performs the specified operation. Result After the operation is completed, status information and other housekeeping information are provided to the microprocessor. The next section introduces each of the commands.
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10.1.6 FDC Commands
Command Symbol Descriptions: C: Cylinder Number 0 - 256 D: Data Pattern DIR: Step Direction DIR = 0: step out DIR = 1: step in DS0: Disk Drive Select 0 DS1: Disk Drive Select 1 DTL: Data Length EC: Enable Count EFIFO: Enable FIFO EIS: Enable Implied Seek EOT: End of Track FIFOTHR: FIFO Threshold GAP: Gap Length Selection GPL: Gap Length H: Head Number HDS: Head Number Select HLT: Head Load Time HUT: Head Unload Time LOCK: Lock EFIFO, FIFOTHR, and PTRTRK bits to prevent being affected by software reset MFM: MFM or FM Mode MT: Multitrack N: The number of data bytes written in a sector NCN: New Cylinder Number ND: Non-DMA Mode OW: Overwritten PCN: Present Cylinder Number POLL: Polling Disable PRETRK: Precompensation Start Track Number R: Record RCN: Relative Cylinder Number R/W: Read/Write SC: Sectors per Cylinder SK: Skip deleted data address mark SRT: Step Rate Time ST0: Status Register 0 ST1: Status Register 1 ST2: Status Register 2 ST3: Status Register 3 WG: Write gate alters timing of WE
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(1) Read Data
PHASE R/W D7 D6 D5 D1 D4 D0 D3 D2 REMARKS
Command
W W W W W W W W W
MT 1 0 HDS
MFM 1 0 DS1 DS0
SK 0 0
0 0
0 Command codes 0 Sector ID information prior to command execution
---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL -----------------------
Execution Result R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------
Data transfer between the FDD and system Status information after command execution Sector ID information after command execution
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(2) Read Deleted Data
PHASE R/W D7 D6 D5 D1 D4 D0 D3 D2 REMARKS
Command
W W W W W W W W W
MT MFM 0 0 0 HDS
SK 0
0 0
1 0
1
Command codes
0 DS1 DS0
---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL -----------------------
Sector ID information prior to command execution
Execution Result R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------
Data transfer between the FDD and system Status information after command execution Sector ID information after command execution
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(3) Read A Track
PHASE R/W D7 D6 D5 D1 D4 D0 D3 D2 REMARKS
Command
W 0 W W W W W W W W
0 0 HDS
MFM 1 0 DS1
0 0 0 DS0
0 0
0 0
Command codes
---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL -----------------------
Sector ID information prior to command execution
Execution
Data transfer between the FDD and system; FDD reads contents of all cylinders from index hole to EOT R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N -----------------------Status information after command execution Sector ID information after command execution
Result
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(4) Read ID
PHASE R/W D7 D6 D5 D1 D4 D0 D3 D2 REMARKS
Command
W 0 W
0 0 HDS
MFM 0 1 0 0 0 DS1 DS0
0 0
1 0
Command codes
Execution
The first correct ID information on the cylinder is stored in the Data Register R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N -----------------------Status information after command execution Disk status after the command has been completed
Result
(5) Verify
PHASE R/W D7 D6 D5 D1 D4 D0 D3 D2 REMARKS
Command
W W W W W W W W
MT 1 EC HDS
MFM SK 1 0 0 0 0 0 0 DS1 DS0 ---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL/SC -------------------
1
Command codes
Sector ID information prior to command execution
Execution Result R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------
No data transfer takes place Status information after command execution Sector ID information after command execution
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(6) Version
PHASE R/W D7 D6 D5 D1 D4 D0 D3 D2 REMARKS
Command Result
W 0 R 0
0 0 1 0
0 0 0 0
0 0
1 1
0 0
Command code Enhanced controller
(7) Write Data
PHASE R/W D7 D6 D5 D1 D4 D0 D3 D2 REMARKS
Command
W 1 W W W W W W W W
MT 0 HDS
MFM 0
0 1 0
0 0
0 0
Command codes
0 DS1 DS0
---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL -----------------------
Sector ID information prior to Command execution
Execution Result R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------
Data transfer between the FDD and the system Status information after Command execution Sector ID information after Command execution
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(8) Write Deleted Data
PHASE R/W D7 D6 D5 D1 D4 D0 D3 D2 REMARKS
Command
W W W W W W W W W
MT 0 0 HDS
MFM 0
0 1 0
0 0
1 0
Command codes
0 DS1 DS0
---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL -----------------------
Sector ID information prior to command execution
Execution Result R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------
Data transfer between the FDD and the system Status information after command execution Sector ID information after command execution
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(9) Format A Track
PHASE R/W D7 D6 D5 D1 D4 D0 D3 D2 REMARKS
Command
W 1 W W W W W
0 0 HDS
MFM 0 0 DS1 DS0
0 1 0
0 0
1 0
Command codes
---------------------- N -------------------------------------------- SC ------------------------------------------- GPL ------------------------------------------ D --------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------- Undefined ---------------------------------- Undefined ---------------------------------- Undefined ---------------------------------- Undefined -------------------
Bytes per Sector Sectors per Cylinder Gap 3 Filler Byte Input Sector Parameters
Execution for Each Sector: (Repeat) Result
W W W W R R R R R R R
Status information after command execution
(10) Recalibrate
PHASE R/W D7 D6 D5 D1 D4 D0 D3 D2 REMARKS
Command
W 1 W 0
0 1 0 DS1
0 1 0 DS0
0 0
0 0
0 0
Command codes
Execution
Head retracted to Track 0 Interrupt
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(11) Sense Interrupt Status
PHASE R/W D7 D6 D5 D1 D4 D0 D3 D2 REMARKS
Command Result
W 0 R R
0
0 0
0 0
0
1
Command code Status information at the end of each seek operation
---------------- ST0 ---------------------------------------- PCN -------------------------
(12) Specify
PHASE R/W D7 D6 D5 D1 D4 D0 D3 D2 REMARKS
Command
W 0 W W
0 1
0 1
0
0
0
Command codes
| ---------SRT ----------- | --------- HUT ---------- | |------------ HLT ----------------------------------| ND
(13) Seek
PHASE R/W D7 D6 D5 D1 D4 D0 D3 D2 REMARKS
Command
W 1 W W
0 1
0 1
0
0
1
Command codes
0 0 0 0 0 HDS DS1 DS0 -------------------- NCN ----------------------Head positioned over proper cylinder on the diskette
Execution
R
(14) Configure
PHASE R/W D7 D6 D5 D1 D4 D0 D3 D2 REMARKS
Command
W 0 W W W
0 1 0
0 1 0 0 EIS
0
1
0
Configure information
0
0 0 0 0 0 EFIFO POLL | ------ FIFOTHR ----| | --------------------PRETRK ----------------------- | Internal registers written
Execution
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(15) Relative Seek
PHASE R/W D7 D6 D5 D1 D4 D0 D3 D2 REMARKS
Command
W 1 W W
1 1
DIR 1
0
0
1
Command codes
0 0 0 0 0 HDS DS1 DS0 | -------------------- RCN ---------------------------- |
(16) Dumpreg
PHASE R/W D7 D6 D5 D1 D4 D0 D3 D2 REMARKS
Command Result
W 1 R R R R R R R R R R
0 1
0 0
0
0
1
Registers placed in FIFO
----------------------- PCN-Drive 0------------------------------------------ PCN-Drive 1 ----------------------------------------- PCN-Drive 2------------------------------------------ PCN-Drive 3 --------------------------SRT ------------------ | --------- HUT ------------------ HLT -----------------------------------| ND ------------------------ SC/EOT ---------------------LOCK 0 D3 D2 D1 D0 GAP WG 0 EIS EFIFO POLL | ------ FIFOTHR ------------------------------PRETRK -------------------------
(17) Perpendicular Mode
PHASE R/W D7 D6 D5 D1 D4 D0 D3 D2 REMARKS
Command
W W
0 0 OW GAP
0 1 0 WG 0 D3
0 D2
1 D1
0 D0
Command Code
(18) Lock
PHASE R/W D7 D6 D5 D1 D4 D0 D3 D2 REMARKS
Command Result
W R
LOCK 1 0 0
0 0 0 0
0 0 0 0
1 LOCK
0 0
Command Code
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(19) Sense Drive Status
PHASE R/W D7 D6 D5 D1 D4 D0 D3 D2 REMARKS
Command
W 1 W
0 0 0 HDS
0 0 0 DS1 DS0
0 0
0 0
0 0
Command Code
Result
R
---------------- ST3 -------------------------
Status information about the disk drive
(20) Invalid
PHASE R/W D7 D6 D5 D1 D4 D0 D3 D2 REMARKS
Command Result
W R
------------- Invalid Codes ------------------------------------ ST0 ----------------------
Invalid codes (no operationFDC goes to standby state) ST0 = 80h
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10.2 Register Descriptions
There are several status, data, and control registers in the W83627DHG. These registers are defined below, and the rest of this section provides more details about each one of them.
ADDRESS OFFSET READ REGISTER WRITE
base address + 0 base address + 1 base address + 2 base address + 3 base address + 4 base address + 5 base address + 7
SA REGISTER SB REGISTER TD REGISTER MS REGISTER DT (FIFO) REGISTER DI REGISTER DO REGISTER TD REGISTER DR REGISTER DT (FIFO) REGISTER CC REGISTER
10.2.1 Status Register A (SA Register) (Read base address + 0)
Along with the SB register, the SA register is used to monitor several disk-interface pins in PS/2 and Model 30 modes. In PS/2 mode, the bit definitions for this register are as follows:
7 6 5 4 3 2 1 0
DIR WP# INDEX# HEAD TRAK0# STEP DRV2# INIT PENDING
INIT PENDING (Bit 7): This bit indicates the value of the floppy disk interrupt output. RESERVED (Bit 6) STEP (Bit 5): This bit indicates the complement of the STEP# output. TRAK0#(Bit 4): This bit indicates the value of the TRAK0# input. HEAD (Bit 3): This bit indicates the complement of the HEAD# output. 0 side 0 1 side 1 Publication Release Date: Aug, 22, 2007 Version 1.4
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INDEX#(Bit 2): This bit indicates the value of the INDEX# output. WP#(Bit 1): 0 disk is write-protected 1 disk is not write-protected DIR (Bit 0) This bit indicates the direction of head movement. 0 outward direction 1 inward direction In PS/2 Model 30 mode, the bit definitions for this register are as follows:
7 6 5 4 3 2 1 0
DIR# WP INDEX HEAD# TRAK0 STEP F/F DRQ INIT PENDING
INIT PENDING (Bit 7): This bit indicates the value of the floppy disk interrupt output. DRQ (Bit 6): This bit indicates the value of the DRQ output pin. STEP F/F (Bit 5): This bit indicates the complement of the latched STEP# output. TRAK0 (Bit 4): This bit indicates the complement of the TRAK0# input. HEAD# (Bit 3): This bit indicates the value of the HEAD# output. 0 side 1 1 side 0 INDEX (Bit 2): This bit indicates the complement of the INDEX# output.
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WP (Bit 1): 0 disk is not write-protected 1 disk is write-protected DIR# (Bit 0) This bit indicates the direction of head movement. 0 inward direction 1 outward direction
10.2.2 Status Register B (SB Register) (Read base address + 1)
Along with the SA register, the SB register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 mode, the bit definitions for this register are as follows:
7 1 6 1 MOT EN A Reserved WE RDATA Toggle WDATA Toggle Drive SEL0 5 4 3 2 1 0
Drive SEL0 (Bit 5): This bit indicates the status of the DO REGISTER, bit 0 (drive-select bit 0). WDATA Toggle (Bit 4): This bit changes state on every rising edge of the WD# output pin. RDATA Toggle (Bit 3): This bit changes state on every rising edge of the RDATA# output pin. WE (Bit 2): This bit indicates the complement of the WE# output pin. RESERVED (Bit 1) MOT EN A (Bit 0) This bit indicates the complement of the MOA# output pin. In PS/2 Model 30 mode, the bit definitions for this register are as follows:
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7
6
5
4
3
2
1
0
DSC# Reserved WE F/F RDATA F/F WD F/F DSA# Reserved Reserved
RESERVED (Bit 7) RESERVED (Bit 6) DSA# (Bit 5): This bit indicates the status of the DSA# output pin. WD F/F (Bit 4): This bit indicates the complement of the WD# output pin, which is latched on every rising edge of the WD# output pin. RDATA F/F (Bit 3): This bit indicates the complement of the latched RDATA# output pin. WE F/F (Bit 2): This bit indicates the complement of the latched WE# output pin. RESERVED (Bit 1) RESERVED (Bit 0)
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10.2.3 Digital Output Register (DO Register) (Write base address + 2)
The Digital Output Register is a write-only register that controls drive motors, drive selection, DRQ/IRQ enable, and FDC reset. The bit definitions are as follows:
7 6 5 4 3 2 1-0 Drive Select: 00 select drive A 01 Reserved 10 Reserved 11 Reserved Floppy Disk Controller Reset Active low resets FDC DMA and INT Enable Active high enable DRQ/IRQ Motor Enable A. Motor A on when active high Reserved Reserved Reserved
10.2.4 Tape Drive Register (TD Register) (Read base address + 3)
This register is used to assign a particular drive number to the tape drive support mode of the data separator. This register also holds the media ID, drive type, and floppy boot drive information for the floppy disk drive. In normal floppy mode, this register only has bits 0 and 1, and the bit definitions are as follows:
7 X 6 X 5 X 4 X 3 X 2 X Tape sel 0 Tape sel 1 1 0
If the three-mode FDD function is enabled (EN3MODE = 1 in LD0 CRF0, Bit 0), the bit definitions are as follows:
7 6 5 4 3 2 1 0
Tape Sel 0 Tape Sel 1 Floppy boot drive 0 Floppy boot drive 1 Drive type ID0 Drive type ID1 Media ID0 Media ID1
Media ID1 Media ID0 (Bit 7, 6): These two bits are read-only. These two bits reflect the value of LD0 CRF1, bits 5 and 4.
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Drive type ID1 Drive type ID0 (Bit 5, 4): These two bits reflect two of the bits in LD0 CRF2. Which two bits are reflected depends on the last drive selection in the DO register. Floppy Boot drive 1, 0 (Bit 3, 2): These two bits reflect the value of LD0 CRF1, bits 7 and 6. Tape Sel 1, Tape Sel 0 (Bit 1, 0): These two bits assign a logical drive number to the tape drive. Drive 0 is not available as a tape drive and is reserved for the floppy disk boot drive.
TAPE SEL 1 TAPE SEL 0 DRIVE SELECTED
0 0 1 1
0 1 0 1
None 1 2 3
10.2.5 Main Status Register (MS Register) (Read base address + 4)
The Main Status Register is used to control the flow of data between the microprocessor and the controller. The bit definitions for this register are as follows:
7 6 5 4 3 2 1 0
FDD 0 Busy, (D0B = 1), FDD number 0 is in the SEEK mode. Reserved. Reserved. Reserved. FDC Busy, (CB). A read or write command is in the process when CB = HIGH. Non-DMA mode, the FDC is in the non-DMA mode, this bit is set only during the execution phase in non-DMA mode. Transition to LOW state indicates execution phase has ended. DATA INPUT/OUTPUT, (DIO). If DIO= HIGH then transfer is from Data Register to the processor. If DIO = LOW then transfer is from processor to Data Register. Request for Master (RQM). A high on this bit indicates Data Register is ready to send or receive data to or from the processor.
10.2.6 Data Rate Register (DR Register) (Write base address + 4)
The Data Rate Register is used to set the transfer rate and write precompensation. However, in PC-AT and PS/2 Model 30 and PS/2 modes, the data rate is controlled by the CC register, not by the DR register. As a result, the real data rate is determined by the most recent write to either the DR or CC register. The bit definitions for this register are as follows:
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7
6
5 0
4
3
2
1
0
DRATE0 DRATE1 PRECOMP0 PRECOMP1 PRECOMP2 POWER DOWN S/W RESET
S/W RESET (Bit 7): This bit is the software reset bit. POWER-DOWN (Bit 6): 0 FDC in normal mode 1 FDC in power-down mode PRECOMP2 PRECOMP1 PRECOMP0 (Bit 4, 3, 2): These three bits select the value of write precompensation. The following tables show the precompensation values for every combination of these bits.
PRECOMP PRECOMPENSATION DELAY
2 0 0 0 0 1 1 1 1
1 0 0 1 1 0 0 1 1
0 0 1 0 1 0 1 0 1
250K - 1 Mbps Default Delays 41.67 ns 83.34 ns 125.00 ns 166.67 ns 208.33 ns 250.00 ns 0.00 ns (disabled)
2 Mbps Tape drive Default Delays 20.8 ns 41.17 ns 62.5ns 83.3 ns 104.2 ns 125.00 ns 0.00 ns (disabled)
DATA RATE
DEFAULT PRECOMPENSATION DELAYS
250 KB/S 300 KB/S 500 KB/S 1 MB/S 2 MB/S
125 ns 125 ns 125 ns 41.67ns 20.8 ns
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DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC and reduced write-current control. 00 01 10 11 500 KB/S (MFM), 250 KB/S (FM), RWC# = 1 300 KB/S (MFM), 150 KB/S (FM), RWC# = 0 250 KB/S (MFM), 125 KB/S (FM), RWC# = 0 1 MB/S (MFM), Illegal (FM), RWC# = 1
The 2 MB/S data rate for the tape drive is only supported by setting DRATE1 and DRATE0 to 01, as well as setting DRT1 and DRT0 (CRF4 and CRF5 for logical device 0) to 10. Please see the functional description of CRF4 or CRF5 and the data rate table for individual data-rate settings.
10.2.7 FIFO Register (R/W base address + 5)
The FIFO register consists of four status registers in a stack, and only one register is presented to the data bus at a time. The FIFO register stores data, commands, and parameters, and it provides disk-drive status information. In addition, data bytes pass through the data register to program or obtain results after a command. In the W83627DHG, this register is disabled after reset. The FIFO can enable it and change its values through the configure command. Status Register 0 (ST0)
7-6 5 4 3 2 1-0
US1, US0 Drive Select: 00 Drive A selected 01 Reserved 10 Reserved 11 Reserved HD Head address: 1 Head selected 0 Head selected NR Not Ready: 1 Drive is not ready 0 Drive is ready EC Equipment Check: 1 When a fault signal is received from the FDD or the track 0 signal fails to occur after 77 step pulses 0 No error SE Seek end: 1 seek end 0 seek error IC Interrupt Code: 00 Normal termination of command 01 Abnormal termination of command 10 Invalid command issue 11 Abnormal termination because the ready signal from FDD changed state during command execution
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Status Register 1 (ST1)
7 6 5 4 3 2 1 0
Missing Address Mark. 1 When the FDC cannot detect the data address mark or the data address mark has been deleted. NW (Not Writable). 1 If a write Protect signal is detected from the diskette drive during execution of write data. ND (No DATA). 1 If specified sector cannot be found during execution of a read, write or verifly data. Not used. This bit is always 0. OR (Over Rum). 1 If the FDC is not serviced by the host system within a certain time interval during data transfer. DE (data Error).1 When the FDC detects a CRC error in either the ID field or the data field. Not used. This bit is always 0. EN (End of track). 1 When the FDC tries to access a sector beyond the final sector of a cylinder.
Status Register 2 (ST2)
7 6 5 4 3 2 1 0
MD (Missing Address Mark in Data Field). 1 If the FDC cannot find a data address mark (or the address mark has been deleted) when reading data from the media 0 No error BC (Bad Cylinder) 1 Bad Cylinder 0 No error SN (Scan Not satisfied) 1 During execution of the Scan command 0 No error SH (Scan Equal Hit) 1 During execution of the Scan command, if the equal condition is satisfied 0 No error WC (Wrong Cylinder) 1 Indicates wrong Cylinder DD (Data error in the Data field) 1 If the FDC detects a CRC error in the data field 0 No error CM (Control Mark) 1 During execution of the read data or scan command 0 No error Not used. This bit is always 0
Status Register 3 (ST3)
7 6 5 4 3 2 1 0
US0 Unit Select 0 US1 Unit Select 1 HD Head Address TS Two-Side TO Track 0 RY Ready WP Write Protected FT Fault
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10.2.8 Digital Input Register (DI Register) (Read base address + 7)
The Digital Input Register is an 8-bit, read-only register used for diagnostic purposes. In PC/XT or PC/AT mode, only bit 7 is checked by the BIOS. When the register is read, bit 7 shows the complement of DSKCHG#, while the other bits remain in tri-state. The bit definitions are as follows:
7 6 5 4 3 2 1 0
xxxxxxx for hard disk controller x Reservedreadthe this register, these bits are in tri-stat During a of
DSKCHG
In PS/2 mode, the bit definitions are as follows:
7 6 1 5 1 4 1 3 1 HIGH DENS# DRATE0 DRATE1 2 1 0
DSKCHG
DSKCHG (Bit 7): This bit indicates the complement of the DSKCHG# input. Bit 6-3: These bits are always a logic 1 during a read. DRATE1 DRATE0 (Bit 2, 1): These two bits select the data rate of the FDC. See DR register bits 1 and 0 (Data Rate Register (DR Register) (Write base address + 4)) for how the settings correspond to individual data rates. HIGHDENS# (Bit 0): 0 500 KB/S or 1 MB/S data rate (high-density FDD) 1 250 KB/S or 300 KB/S data rate In PS/2 Model 30 mode, the bit definitions are as follows:
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7
6 0
5 0
4 0
3
2
1
0
DRATE0 DRATE1 NOPREC DMAEN
DSKCHG#
DSKCHG (Bit 7): This bit indicates the status of the DSKCHG# input. Bit 6-4: These bits are always a logic 0 during a read. DMAEN (Bit 3): This bit indicates the value of DO register, bit 3. NOPREC (Bit 2): This bit indicates the value of the NOPREC bit in the CC REGISTER. DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC. See DR register bits 1 and 0 (Data Rate Register (DR Register) (Write base address + 4)) for how the settings correspond to individual data rates.
10.2.9 Configuration Control Register (CC Register) (Write base address + 7)
This register is used to control the data rate. In PC/AT and PS/2 mode, the bit definitions are as follows:
7 6 5 4 3 2 1 0
x
x
x
x
x
x
DRATE0 DRATE1
X: Reserved Bit 7-2: Reserved. These bits should be set to 0. DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC. See DR register bits 1 and 0 (Data Rate Register (DR Register) (Write base address + 4)) for how the settings correspond to individual data rates.
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In the PS/2 Model 30 mode, the bit definitions are as follows:
7 X 6 X 5 X 4 X 3 X DRATE0 DRATE1 NOPREC 2 1 0
X: Reserved Bit 7-3: Reserved. These bits should be set to 0. NOPREC (Bit 2): This bit disables the precompensation function. It can be set by the software. DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC. See DR register bits 1 and 0 (Data Rate Register (DR Register) (Write base address + 4)) for how the settings correspond to individual data rates.
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11. UART PORT 11.1 Universal Asynchronous Receiver/Transmitter (UART A, UART B)
The UARTs are used to convert parallel data into serial format for transmission and to convert serial data into parallel format during reception. The serial data format is a start bit, followed by five to eight data bits, a parity bit (if programmed) and one, one-and-a-half (five-bit format only) or two stop bits. The UARTs are capable of handling divisors of 1 to 65535 and producing a 16x clock for driving the internal transmitter logic. Provisions are also included to use this 16x clock to drive the receiver logic. The UARTs also support the MIDI data rate. Furthermore, the UARTs also include a complete modem control capability and 16-byte FIFOs for reception and transmission to reduce the number of interrupts presented to the CPU.
11.2 Register Description
11.2.1 UART Control Register (UCR) (Read/Write)
The UART Control Register defines and controls the protocol for asynchronous data communication, including data length, stop bit, parity, and baud rate selection.
7 6 5 4 3 2 1 0
Data length select bit 0 (DLS0) Data length select bit 1(DLS1) Multiple stop bits enable (MSBE) Parity bit enable (PBE) Even parity enable (EPE) Parity bit fixed enable (PBFE) Set silence enable (SSE) Baudrate divisor latch access bit (BDLAB)
Bit 7: BDLAB. When this bit is set to logical 1, designers can access the divisor (in 16-bit binary format) from the divisor latches of the baud-rate generator during a read or write operation. When this bit is set to logical 0, the Receiver Buffer Register, the Transmitter Buffer Register, and the Interrupt Control Register can be accessed. Bit 6: SSE. A logical 1 forces the Serial Output (SOUT) to a silent state (a logical 0). Only IRTX is affected by this bit; the transmitter is not affected. Bit 5: PBFE. When PBE and PBFE of UCR are both set to logical 1, (1) if EPE is logical 1, the parity bit is fixed as logical 0 when transmitting and checking. (2) if EPE is logical 0, the parity bit is fixed as logical 1 when transmitting and checking. Bit 4: EPE. When PBE is set to logical 1, this bit counts the number of logical 1's in the data word bits and determines the parity bit. When this bit is set to logical 1, the parity bit is set to logical 1 if an even number of logical 1's are sent or checked. When the bit is set to logical 0, the parity bit is logical 1 if an odd number of logic 1's are sent or checked. Bit 3: PBE. When this bit is set to logical 1, the transmitter inserts a stop bit between the last data bit and the stop bit of the SOUT, and the receiver checks the parity bit in the same position.
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Bit 2: MSBE. This bit defines the number of stop bits in each serial character that is transmitted or received. (1) If MSBE is set to logical 0, one stop bit is sent and checked. (2) If MSBE is set to logical 1 and the data length is 5 bits, one-and-a-half stop bits are sent and checked. (3) If MSBE is set to logical 1 and the data length is 6, 7, or 8 bits, two stop bits are sent and checked. Bits 0 and 1: DLS0, DLS1. These two bits define the number of data bits that are sent or checked in each serial character.
DLS1 DLS0 DATA LENGTH
0 0 1 1
0 1 0 1
5 bits 6 bits 7 bits 8 bits
The following table identifies the remaining UART registers. Each one is described separately in the following sections.
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Bit Number
Register Address Base
+0 BDLAB = 0 Receiver Buffer Register (Read Only) Transmitter Buffer Register (Write Only) Interrupt Control Register Interrupt Status Register (Read Only) UART FIFO Control Register (Write Only) UART Control Register Handshake Control Register RBR
0
1
2
RX Data Bit 2
3
RX Data Bit 3
4
RX Data Bit 4
5
6
7
RX Data RX Data Bit 0 Bit 1
RX Data RX Data RX Data Bit 5 Bit 6 Bit 7
+0 BDLAB = 0
TBR
TX Data Bit 0
TX Data Bit 1
TX Data Bit 2 USR Interrupt Enable (EUSRI) Interrupt Status Bit (1) XMIT FIFO Reset Multiple Stop Bits Enable (MSBE) Loopback RI Input Parity Bit Error (PBER) RI Falling Edge (FERI) Bit 2 Bit 2
TX Data Bit 3 HSR Interrupt Enable (EHSRI) Interrupt Status Bit (2)** DMA Mode Select Parity Bit Enable (PBE) IRQ Enable No Stop Bit Error (NSER) DCD Toggling (TDCD) Bit 3 Bit 3
TX Data Bit 4
TX Data Bit 5
TX Data Bit 6
TX Data Bit 7
+1 BDLAB = 0
ICR
RBR Data TBR Ready Empty Interrupt Interrupt Enable Enable (ERDRI) (ETBREI) "0" if Interrupt Pending Interrupt Status Bit (0) RCVR FIFO Reset Data Length Select Bit 1 (DLS1) Request to Send (RTS) Overrun Error (OER) DSR Toggling (TDSR) Bit 1 Bit 1
0
0
0
0
+2
ISR
0
0
FIFOs Enabled ** RX Interrupt Active Level (LSB) Set Silence Enable (SSE)
FIFOs Enabled ** RX Interrupt Active Level (MSB) Baudrate Divisor Latch Access Bit (BDLAB) 0 RX FIFO Error Indication (RFEI) ** Data Carrier Detect (DCD) Bit 7 Bit 7
+2
UFR
FIFO Enable Data Length Select Bit 0 (DLS0) Data Terminal Ready (DTR) RBR Data Ready (RDR) CTS Toggling (TCTS) Bit 0 Bit 0
Reserved Reversed
+3
UCR
Even Parity Enable (EPE) Internal Loopback Enable Silent Byte Detected (SBD) Clear to Send (CTS) Bit 4 Bit 4
Parity Bit Fixed Enable PBFE)
+4
HCR
0
0
+5
UART Status USR Register Handshake Status Register
TBR Empty (TBRE) Data Set Ready (DSR) Bit 5 Bit 5
TSR Empty (TSRE) Ring Indicator (RI) Bit 6 Bit 6
+6
HSR
+7
User Defined UDR Register BLL
Baudrate +0 Divisor Latch BDLAB = 1 Low Baudrate +1 Divisor Latch BDLAB = 1 High
BHL
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received. **: These bits are always 0 in 16450 Mode.
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11.2.2 UART Status Register (USR) (Read/Write)
This 8-bit register provides information about the status of data transfer during communication.
7 6 5 4 3 2 1 0
RBR Data ready (RDR) Overrun error (OER) Parity bit error (PBER) No stop bit error (NSER) Silent byte detected (SBD) Transmitter Buffer Register empty (TBRE) Transmitter Shift Register empty (TSRE) RX FIFO Error Indication (RFEI)
Bit 7: RFEI. In 16450 mode, this bit is always set to logical 0. In 16550 mode, this bit is set to logical 1 when there is at least one parity-bit error and no stop-bit error or silent-byte detected in the FIFO. In 16550 mode, this bit is cleared to logical 0 by reading from the USR if there are no remaining errors left in the FIFO. Bit 6: TSRE. In 16450 mode, this bit is set to logical 1 when TBR and TSR are both empty. In 16550 mode, it is set to logical 1 when the transmit FIFO and TSR are both empty. Otherwise, this bit is set to logical 0. Bit 5: TBRE. In 16450 mode, when a data character is transferred from TBR to TSR, this bit is set to logical 1. If ETREI of ICR is high, an interrupt is generated to notify the CPU to write the next data. In 16550 mode, this bit is set to logical 1 when the transmit FIFO is empty. It is set to logical 0 when the CPU writes data into TBR or the FIFO. Bit 4: SBD. This bit is set to logical 1 to indicate that received data are kept in silent state for the time it takes to receive a full word, which includes the start bit, data bits, parity bit, and stop bits. In 16550 mode, it indicates the same condition for the data on the top of the FIFO. When the CPU reads USR, it sets this bit to logical 0. Bit 3: NSER. This bit is set to logical 1 to indicate that the received data have no stop bit. In 16550 mode, it indicates the same condition for the data on the top of the FIFO. When the CPU reads USR, it sets this bit to logical 0. Bit 2: PBER. This bit is set to logical 1 to indicate that the received data has the wrong parity bit. In 16550 mode, it indicates the same condition for the data on the top of the FIFO. When the CPU reads USR, it sets this bit to logical 0. Bit 1: OER. This bit is set to logical 1 to indicate that the received data have been overwritten by the next received data before they were read by the CPU. In 16550 mode, it indicates the same condition, instead of FIFO full. When the CPU reads USR, it sets this bit to logical 0. Bit 0: RDR. This bit is set to logical 1 to indicate that the received data are ready to be read by the CPU in the RBR or FIFO. When no data are left in the RBR or FIFO, the bit is set to logical 0.
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11.2.3 Handshake Control Register (HCR) (Read/Write)
This register controls pins used with handshaking peripherals such as modems and also controls the diagnostic mode of the UART.
7 0 6 0 5 0 Data terminal ready (DTR) Request to send (RTS) Loopback RI input IRQ enable Internal loopback enable 4 3 2 1 0
Bit 4: When this bit is set to logical 1, the UART enters diagnostic mode, as follows: (1) SOUT is forced to logical 1, and SIN is isolated from the communication link. (2) The modem output pins are set to their inactive state. (3) The modem input pins are isolated from the communication link and connect internally as DTR (bit 0 of HCR)DSR#, RTS (bit 1 of HCR) CTS#, Loopback RI input (bit 2 of HCR) RI# and IRQ enable (bit 3 of HCR) DCD#. Aside from the above connections, the UART operates normally. This method allows the CPU to test the UART in a convenient way. Bit 3: The UART interrupt output is enabled by setting this bit to logical 1. In diagnostic mode, this bit is internally connected to the modem control input DCD#. Bit 2: This bit is only used in the diagnostic mode. In diagnostic mode, this bit is internally connected to the modem control input RI#. Bit 1: This bit controls the RTS# output. The value of this bit is inverted and output to RTS#. Bit 0: This bit controls the DTR# output. The value of this bit is inverted and output to DTR#.
11.2.4 Handshake Status Register (HSR) (Read/Write)
This register reflects the current state of the four input pins used with handshake peripherals such as modems and records changes on these pins.
7 6 5 4 3 2 1 0
CTS# toggling (TCTS) DSR# toggling (TDSR) RI falling edge (FERI) DCD# toggling (TDCD) Clear to send (CTS) Data set ready (DSR) Ring indicator (RI) Data carrier detect (DCD)
Bit 7: This bit is the opposite of the DCD# input. This bit is equivalent to bit 3 of HCR in loopback mode. Bit 6: This bit is the opposite of the RI # input. This bit is equivalent to bit 2 of HCR in loopback mode. Bit 5: This bit is the opposite of the DSR# input. This bit is equivalent to bit 0 of HCR in loopback mode. Bit 4: This bit is the opposite of the CTS# input. This bit is equivalent to bit 1 of HCR in loopback mode.
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Bit 3: TDCD. This bit indicates that the DCD# pin has changed state after HSR was read by the CPU. Bit 2: FERI. This bit indicates that the RI # pin has changed from low to high after HSR was read by the CPU. Bit 1: TDSR. This bit indicates that the DSR# pin has changed state after HSR was read by the CPU. Bit 0: TCTS. This bit indicates that the CTS# pin has changed state after HSR was read by the CPU.
11.2.5 UART FIFO Control Register (UFR) (Write only)
This register is used to control the FIFO functions of the UART.
7 6 5 4 3 2 1 0
FIFO enable Receiver FIFO reset Transmitter FIFO reset DMA mode select Reserved Reserved RX interrupt active level (LSB) RX interrupt active level (MSB)
Bit 6, 7: These two bits are used to set the active level of the receiver FIFO interrupt. The active level is the number of bytes that must be in the receiver FIFO to generate an interrupt.
BIT 7 BIT 6 RX FIFO INTERRUPT ACTIVE LEVEL (BYTES)
0 0 1 1
0 1 0 1
01 04 08 14
Bit 4, 5: Reserved Bit 3: When this bit is set to logical 1, DMA mode changes from mode 0 to mode 1 if UFR bit 0 = 1. Bit 2: Setting this bit to logical 1 resets the TX FIFO counter logic to its initial state. This bit is automatically cleared afterwards. Bit 1: Setting this bit to logical 1 resets the RX FIFO counter logic to its initial state. This bit is automatically cleared afterwards. Bit 0: This bit enables 16550 (FIFO) mode. This bit should be set to logical 1 before the other UFR bits are programmed.
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11.2.6 Interrupt Status Register (ISR) (Read only)
This register reflects the UART interrupt status.
7 6 5 0 4 0 0 if interrupt pending Interrupt Status bit 0 Interrupt Status bit 1 Interrupt Status bit 2 FIFOs enabled FIFOs enabled 3 2 1 0
Bit 7, 6: These two bits are set to logical 1 when UFR, bit 0 = 1. Bit 5, 4: These two bits are always logical 0. Bit 3: In 16450 mode, this bit is logical 0. In 16550 mode, bits 3 and 2 are set to logical 1 when a time-out interrupt is pending. See the table below. Bit 2, 1: These two bits identify the priority level of the pending interrupt, as shown in the table below. Bit 0: This bit is logical 1 if there is no interrupt pending. If one of the interrupt sources has occurred, this bit is set to logical 0.
ISR
Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 1 0 1 1 0 Interrupt priority First Interrupt Type UART Receive Status RBR Data Ready
INTERRUPT SET AND FUNCTION
Interrupt Source No Interrupt pending 1. OER = 1 3. NSER = 1 2. PBER =1 4. SBD = 1 Read USR 1. Read RBR 2. Read RBR until FIFO data under active level Read RBR 1. Write data into TBR 2. Read ISR (if priority is third) 2. TDSR = 1 4. TDCD = 1 Read HSR Clear Interrupt -
0
1
0
0
Second
1. RBR data ready 2. FIFO interrupt active level reached Data present in RX FIFO for 4 characters period of time since last access of RX FIFO. TBR empty 1. TCTS = 1 3. FERI = 1
1
1
0
0
Second
FIFO Data Timeout
0
0
1
0
Third
TBR Empty
0
0
0
0
Fourth
Handshake status
** Bit 3 of ISR is enabled when bit 0 of UFR is logical 1.
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11.2.7 Interrupt Control Register (ICR) (Read/Write)
This 8-bit register enables and disables the five types of controller interrupts separately. A selected interrupt can be enabled by setting the appropriate bit to logical 1. The interrupt system can be totally disabled by setting bits 0 through 3 to logical 0.
7 0 6 0 5 0 4 0 RBR data ready interrupt enable (ERDRI) TBR empty interrupt enable (ETBREI) UART receive status interrupt enable (EUSRI) Handshake status interrupt enable (EHSRI) 3 2 1 0
Bit 7-4: These four bits are always logical 0. Bit 3: EHSRI. Set this bit to logical 1 to enable the handshake status register interrupt. Bit 2: EUSRI. Set this bit to logical 1 to enable the UART status register interrupt. Bit 1: ETBREI. Set this bit to logical 1 to enable the TBR empty interrupt. Bit 0: ERDRI. Set this bit to logic 1 to enable the RBR data ready interrupt.
11.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write)
Two 8-bit registers, BLL and BHL, compose a programmable baud generator that uses 24 MHz to generate a 1.8461 MHz frequency and divide it by a divisor from 1 to (216 -1). The output frequency of the baud generator is the baud rate multiplied by 16, and this is the base frequency for the transmitter and receiver. The table below illustrates the use of the baud generator with a frequency of 1.8461 MHz. In high-speed UART mode (CR0C, bits 7 and 6), the programmable baud generator directly uses 24 MHz and the same divisor as the normal speed divisor. As a result, in high-speed mode, the data transmission rate can be as high as 1.5M bps.
BAUD RATE FROM DIFFERENT PRE-DIVIDER PRE-DIV: 13 1.8461M HZ PRE-DIV:1.625 PRE-DIV: 1.0 14.769M HZ 24M HZ DECIMAL DIVISOR USED TO GENERATE 16X CLOCK
ERROR PERCENTAGE
50 75 110 134.5 150 300 600 1200 1800 2000
400 600 880 1076 1200 2400 4800 9600 14400 16000
650 975 1430 1478.5 1950 3900 7800 15600 23400 26000
2304 1536 1047 857 768 384 192 96 64 58
** ** 0.18% 0.099% ** ** ** ** ** 0.53%
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Continued.
BAUD RATE FROM DIFFERENT PRE-DIVIDER PRE-DIV: 13 1.8461M HZ PRE-DIV:1.625 PRE-DIV: 1.0 14.769M HZ 24M HZ DECIMAL DIVISOR USED TO GENERATE 16X CLOCK
ERROR PERCENTAGE
2400 3600 4800 7200 9600 19200 38400 57600 115200
19200 28800 38400 57600 76800 153600 307200 460800 921600
31200 46800 62400 93600 124800 249600 499200 748800 1497600
48 32 24 16 12 6 3 2 1
** ** ** ** ** ** ** ** **
** Unless specified, the error percentage for all of the baud rates is 0.16%. Note: Pre-Divisor is determined by CRF0 of UART A and B.
11.2.9 User-defined Register (UDR) (Read/Write)
This is a temporary register that can be accessed and defined by the user.
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12. PARALLEL PORT 12.1 Printer Interface Logic
The W83627DHG parallel port can be attached to devices that accept eight bits of parallel data at standard TTL level. The W83627DHG supports the IBM XT/AT compatible parallel port (SPP), the bi-directional parallel port (BPP), the Enhanced Parallel Port (EPP), and the Extended Capabilities Parallel Port (ECP) on the parallel port. The following tables show the pin definitions for different modes of the parallel port.
HOST CONNECTOR
1 2-9 10 11 12 13 14 15 16 17
PIN NUMBER OF W83627DHG
36 31-26, 24-23 22 21 19 18 35 34 33 32
PIN ATTRIBUTE
O I/O I I I I O I O O
SPP
nSTB PD<0:7> nACK BUSY PE SLCT nAFD nERR nINIT nSLIN
EPP
nWrite PD<0:7> Intr nWait PE Select nDStrb nError nInit nAStrb
ECP
nSTB, HostClk2 PD<0:7> nACK, PeriphClk2 BUSY, PeriphAck2 PEerror, nAckReverse2 SLCT, Xflag2 nAFD, HostAck2 nFault1, nPeriphRequest2 nINIT1, nReverseRqst2 nSLIN1 , ECPMode2
Notes: n : Active Low 1. Compatible Mode 2. High Speed Mode 3. For more information, please refer to the IEEE 1284 standard.
HOST CONNECTOR
PIN NUMBER OF W83627DHG
PIN ATTRIBUTE
SPP
1 2 3 4 5 6 7 8 9 10 11
36 31 30 29 28 27 26 24 23 22 21
O I/O I/O I/O I/O I/O I/O I/O I/O I I
nSTB PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 nACK BUSY
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Continued
HOST CONNECTOR
PIN NUMBER OF W83627DHG
PIN ATTRIBUTE
SPP
12 13 14 15 16 17
19 18 35 34 33 32
I I O I O O
PE SLCT nAFD nERR nINIT nSLIN
12.2 Enhanced Parallel Port (EPP)
The following table lists the registers used in the EPP mode and identifies the bit map of the parallel port and EPP registers. Some of the registers are used in other modes as well.
A2 A1 A0 REGISTER NOTE
0 0 0 0 0 1 1 1 1
0 0 1 1 1 0 0 1 1
0 1 0 0 1 0 1 0 1
Data port (R/W) Printer status buffer (Read) Printer control latch (Write) Printer control swapper (Read) EPP address port (R/W) EPP data port 0 (R/W) EPP data port 1 (R/W) EPP data port 2 (R/W) EPP data port 2 (R/W)
1 1 1 1 2 2 2 2 2
Notes: 1. These registers are available in all modes. 2. These registers are available only in EPP mode.
REGISTER
Data Port (R/W) Status Buffer (Read) Control Swapper (Read) Control Latch (Write) EPP Address Port R/W) EPP Data Port 0 (R/W) EPP Data Port 1 (R/W)
7
PD7
6
PD6
5
PD5 PE 1 DIR PD5 PD5 PD5 PD5 PD5
4
PD4 SLCT IRQEN IRQ PD4 PD4 PD4 PD4 PD4 PD3
3
ERROR# SLIN SLIN PD3 PD3 PD3 PD3 PD3 1
2
PD2 1
1
PD1 PD0
0
TMOUT
BUSY# ACK# 1 1 PD7 PD7 PD7 PD7 PD7 1 1 PD6 PD6 PD6 PD6 PD6
INIT# INIT# PD2 PD2 PD2 PD2 PD2
AUTOFD# STROBE# AUTOFD# STROBE# PD1 PD1 PD1 PD1 PD1 PD0 PD0 PD0 PD0 PD0
EPP Data Port 2 (R/W) EPP Data Port 3 (R/W)
Each register (or pair of registers, in some cases) is discussed below.
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12.2.1 Data Port (Data Swapper)
The CPU reads the contents of the printer's data latch by reading the data port.
12.2.2 Printer Status Buffer
The CPU reads the printer status by reading the printer status buffer. The bit definitions are as follows:
7 6 5 4 3 2 1 1 1 TMOUT ERROR# SLCT PE ACK# BUSY# 0
Bit 7: This signal is active during data entry, when the printer is off-line during printing, when the print head is changing position, or in an error state. When this signal is active, the printer is busy and cannot accept data. Bit 6: This bit represents the current state of the printer's ACK# signal. A logical 0 means the printer has received a character and is ready to accept another. Normally, this signal is active for approximately 5 s before BUSY# stops. Bit 5: A logical 1 means the printer has detected the end of paper. Bit 4: A logical 1 means the printer is selected. Bit 3: A logical 0 means the printer has encountered an error condition. Bit 1, 2: Reserved. These two bits are always read as logical 1. Bit 0: This bit is only valid in EPP mode. A logical 1 indicates that a 10-s time-out has occurred on the EPP bus; a logical 0 means that no time-out error has occurred. Writing a logical 1 to this bit clears the time-out status bit; writing a logical 0 has no effect.
12.2.3 Printer Control Latch and Printer Control Swapper
The CPU reads the contents of the printer control latch by reading the printer control swapper. The bit definitions are as follows:
7 1 6 1 STROBE AUTO FD INIT# SLCT IN IRQ ENABLE DIR 5 4 3 2 1 0
Bit 7, 6: These two bits are always read as logical 1. They can be written. Bit 5: Direction control bit
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When this bit is logical 1, the parallel port is in input mode (read); when it is logical 0, the parallel port is in output mode (write). This bit can be read and written. In SPP mode, this bit is invalid and fixed at zero. Bit 4: A logical 1 allows an interrupt to occur when ACK# changes from low to high. Bit 3: A logical 1 selects the printer. Bit 2: A logical 0 starts the printer (50 microsecond pulse, minimum). Bit 1: A logical 1 causes the printer to line-feed after a line is printed. Bit 0: A logical 1 generates an active-high pulse for a minimum of 0.5s to clock data into the printer. Valid data must be present for a minimum of 0.5s before and after the strobe pulse.
12.2.4 EPP Address Port
The address port is available only in EPP mode. Bit definitions are as follows:
7 6 5 4 3 2 1 0
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7
The contents of DB0-DB7 are buffered (non-inverting) and output to ports PD0-PD7 during a write operation. The leading edge of IOW# causes an EPP address write cycle to be performed, and the trailing edge of IOW# latches the data for the duration of the EPP write cycle. PD0-PD7 ports are read during a read operation. The leading edge of IOR# causes an EPP address read cycle to be performed and the data to be output to the host CPU.
12.2.5 EPP Data Port 0-3
These four registers are available only in EPP mode. The bit definitions for each data port are the same and as follows:
7 6 5 4 3 2 1 0
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7
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When any EPP data port is accessed, the contents of DB0-DB7 are buffered (non-inverting) and output to ports PD0-PD7 during a write operation. The leading edge of IOW# causes an EPP data write cycle to be performed, and the trailing edge of IOW# latches the data for the duration of the EPP write cycle. During a read operation, ports PD0-PD7 are read, and the leading edge of IOR# causes an EPP read cycle to be performed and the data to be output to the host CPU.
12.2.6 EPP Pin Descriptions
EPP NAME TYPE EPP DESCRIPTION
NWrite PD<0:7> Intr NWait PE Select NDStrb Nerror Ninits NAStrb
O I/O I I I I O I O O
Denotes read or write operation for address or data. Bi-directional EPP address and data bus. Used by peripheral device to interrupt the host. Inactivated to acknowledge that data transfer is complete. Activated to indicate that the device is ready for the next transfer. Paper end; same as SPP mode. Printer-select status; same as SPP mode. This signal is active low. It denotes a data read or write operation. Error; same as SPP mode. This signal is active low. When it is active, the EPP device is reset to its initial operating mode. This signal is active low. It denotes an address read or write operation.
12.2.7 EPP Operation
When EPP mode is selected, the PDx bus is in standard or bi-directional mode when no EPP read, write, or address cycle is being executed. In this situation, all output signals are set by the SPP Control Port and the direction is controlled by DIR of the Control Port. A watchdog timer is required to prevent system lockup. The timer indicates that more than 10 s have elapsed from the start of the EPP cycle to the time WAIT# is deasserted. The current EPP cycle is aborted when a time-out occurs. The time-out condition is indicated in status bit 0. The EPP operates on a two-phase cycle. First, the host selects the register within the device for subsequent operations. Second, the host performs a series of read and/or write byte operations to the selected register. Four operations are supported on the EPP: Address Write, Data Write, Address Read, and Data Read. All operations on the EPP device are performed asynchronously. 12.2.7.1. EPP Version 1.9 Operation The EPP read/write operation can be completed under the following conditions: a. If nWait is active low, the read cycle (nWrite inactive high, nDStrb/nAStrb active low) or write cycle (nWrite active low, nDStrb/nAStrb active low) starts, proceeds normally, and is completed when nWait goes inactive high. b. If nWait is inactive high, the read/write cycle cannot start. It must wait until nWait changes to active low, at which time it starts as described above.
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12.2.7.2. EPP Version 1.7 Operation The EPP read/write cycle can start without checking whether nWait is active or inactive. Once the read/write cycle starts; however, it does not finish until nWait changes from active low to inactive high.
12.3 Extended Capabilities Parallel (ECP) Port
This port is software- and hardware-compatible with existing parallel ports, so the W83627DHG parallel port may be used in standard printer mode if ECP is not required. It provides an automatic high burst-bandwidth channel that supports DMA for ECP in both the forward (host-to-peripheral) and reverse (peripheral-to-host) directions. Small FIFOs are used in both forward and reverse directions to improve the maximum bandwidth requirement. The size of the FIFO is 16 bytes. The ECP port supports an automatic handshake for the standard parallel port to improve compatibility mode transfer speed. The ECP port hardware supports run-length-encoded (RLE) decompression. Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is to be repeated. RLE compression is required; the hardware support is optional. For more information about the ECP Protocol, please refer to the Extended Capabilities Port Protocol and ISA Interface Standard. The W83627DHG ECP supports the following modes.
MODE DESCRIPTION
000 001 010 011 100 101 110 111
SPP mode PS/2 Parallel Port mode Parallel Port Data FIFO mode ECP Parallel Port mode EPP mode (If this option is enabled in the CRF0 to select ECP/EPP mode) Reserved Test mode Configuration mode
The mode selection bits are bits 7-5 of the Extended Control Register.
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12.3.1 ECP Register and Bit Map
The next two tables list the registers used in the ECP mode and provide a bit map of the parallel port and ECP registers.
NAME
ADDRESS
I/O
ECP MODES
FUNCTION
data ecpAFifo dsr dcr cFifo ecpDFifo tFifo cnfgA cnfgB ecr
Base+000h Base+000h Base+001h Base+002h Base+400h Base+400h Base+400h Base+400h Base+401h Base+402h
R/W R/W R R/W R/W R/W R/W R R/W R/W
000-001 011 All All 010 011 110 111 111 All
Data Register ECP FIFO (Address) Status Register Control Register Parallel Port Data FIFO ECP FIFO (DATA) Test FIFO Configuration Register A Configuration Register B Extended Control Register
Note: The base addresses are specified by CR60 and 61, which are determined by the configuration register or the hardware setting.
D7
D6
PD6
D5
PD5
D4
PD4
D3
PD3
D2
PD2
D1
PD1
D0
PD0
NOTE
2
Data ecpAFifo Dsr Dcr cFifo ecpDFifo tFifo cnfgA cnfgB Ecr
PD7 Addr/RLE nBusy 1
Address or RLE field nAck 1 PError Directio Select ackIntEn nFault SelectIn 1 nInit 1 autofd 1 strobe
1 1 2 2 2
Parallel Port Data FIFO ECP Data FIFO Test FIFO 0 compress 0 intrValue MODE 0 1 1 1 nErrIntrEn 0 1 dmaEn 0 1 serviceIntr 0 1 full 0 1 empty
Notes: 1. These registers are available in all modes. 2. All FIFOs use one common 16-byte FIFO.
Each register (or pair of registers, in some cases) is discussed below.
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12.3.2 Data and ecpAFifo Port
Modes 000 (SPP) and 001 (PS/2) (Data Port) During a write operation, the Data Register latches the contents of the data bus on the rising edge of the input, and the contents of this register are output to PD0-PD7. During a read operation, ports PD0-PD7 are read and output to the host. The bit definitions are as follows:
7 6 5 4 3 2 1 0
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7
Mode 011 (ECP FIFO-Address/RLE) A data byte written to this address is placed in the FIFO and tagged as an ECP Address/RLE. The hardware at the ECP port transmits this byte to the peripheral automatically. This operation is defined only for the forward direction. The bit definitions are as follows:
7 6 5 4 3 2 1 0
Address or RLE Address/RLE
12.3.3 Device Status Register (DSR)
These bits are logical 0 during a read of the Printer Status Register. The bits of this status register are defined as follows:
7 6 5 4 3 2 1 1 1 0 1
nFault Select PError nAck nBusy
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Bit 7: This bit reflects the complement of the Busy input. Bit 6: This bit reflects the nAck input. Bit 5: This bit reflects the PError input. Bit 4: This bit reflects the Select input. Bit 3: This bit reflects the nFault input. Bit 2-0: These three bits are not implemented and are always logical 1 during a read.
12.3.4 Device Control Register (DCR)
The bit definitions are as follows:
7 1 6 1 strobe autofd nInit SelectIn ackIntEn Direction 5 4 3 2 1 0
Bit 7, 6: These two bits are always read as logical one and cannot be written. Bit 5: If the mode is 000 or 010, this bit has no effect and the direction is always out. In other modes, 0 the parallel port is in output mode. 1 the parallel port is in input mode. Bit 4: Interrupt request enable. When this bit is set to logical 1, it enables interrupt requests from the parallel port to the CPU on the low-to-high transition on ACK#. Bit 3: This bit is inverted and output to the SLIN# output. 0 The printer is not selected. 1 The printer is selected. Bit 2: This bit is output to the INIT# output. Bit 1: This bit is inverted and output to the AFD# output. Bit 0: This bit is inverted and output to the STB# output.
12.3.5 CFIFO (Parallel Port Data FIFO) Mode = 010
This mode is defined only for the forward direction. Bytes written or DMAed to this FIFO are transmitted by a hardware handshake to the peripheral using the standard parallel port protocol. Transfers to the FIFO are byte-aligned.
12.3.6 ECPDFIFO (ECP Data FIFO) Mode = 011
When the direction bit is 0, bytes written or DMAed to this FIFO are transmitted by a hardware handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are byte-aligned. When the direction bit is 1, data bytes from the peripheral are read via automatic hardware handshake from ECP into this FIFO. Reads or DMAs from the FIFO return bytes of ECP data to the system.
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12.3.7 TFIFO (Test FIFO Mode) Mode = 110
Data bytes may be read, written, or DMAed to or from the system to this FIFO in any direction. Data in the tFIFO is not transmitted to the parallel port lines. However, data in the tFIFO may be displayed on the parallel port data lines.
12.3.8 CNFGA (Configuration Register A) Mode = 111
This register is a read-only register. When it is read, 10h is returned indicating an 8-bit implementation.
12.3.9 CNFGB (Configuration Register B) Mode = 111
The bit definitions are as follows:
7 6 5 4 3 2 1 1 1 0 1
IRQx 0 IRQx 1 IRQx 2 intrValue compress
Bit 7: This bit is read-only. It is logical 0 during a read, which means that this chip does not support hardware RLE compression. Bit 6: Returns the value on the ISA IRQ line to determine possible conflicts. Bit 5-3: Reflects the IRQ resource assigned for ECP port.
CNFGB[5:3] IRQ RESOURCE
000 001 010 011 100 101 110 111
Reflects other IRQ resources selected by PnP register (default) IRQ7 IRQ9 IRQ10 IRQ11 IRQ14 IRQ15 IRQ5
Bit 2-0: These five bits are logical 1 during a read and can be written.
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12.3.10 ECR (Extended Control Register) Mode = all
This register controls the extended ECP parallel port functions. The bit definitions are follows: 7 6 5 4 3 2 1 0
empty full service Intr dmaEn nErrIntrEn MODE MODE MODE
Bit 7-5: Read/Write. These bits select the mode. 000 Standard Parallel Port (SPP) mode. The FIFO is reset in this mode. 001 PS/2 Parallel Port mode. In addition to the functions of the SPP mode, this mode has an extra trait: Direction is able to tri-state the data lines. Furthermore, reading the data register returns the value on the data lines, not the value in the data register. 010 Parallel Port FIFO mode. This is the same as SPP mode except that bytes are written or DMAed to the FIFO. FIFO data are automatically transmitted using the standard parallel port protocol. This mode functions only when direction is 0. 011 ECP Parallel Port Mode. When the direction is 0 (forward direction), bytes placed into the ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFO and automatically transmitted to the peripheral using the ECP Protocol. When the direction is 1 (reverse direction), bytes are moved from the ECP parallel port and packed into bytes in the ecpDFifo. 100 EPP Mode. EPP mode is activated if the EPP mode is selected. 101 Reserved. 110 Test Mode. The FIFO may be written and read in this mode, but the data is not transmitted on the parallel port. 111 Configuration Mode. The confgA and confgB registers are accessible at 0x400 and 0x401 in this mode. Bit 4: Read/Write (Valid only in ECP Mode) 1 Disables the interrupt generated on the asserting edge of nFault. 0 Enables the interrupt generated on the falling edge of nFault. This prevents interrupts from being lost in the time between the read of the ECR and the write of the ECR. Bit 3: Read/Write 1 Enables DMA. 0 Disables DMA unconditionally.
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Bit 2: Read/Write 1 Disables DMA and all of the service interrupts. Writing a logical 1 to this bit does not cause an interrupt. 0 Enables one of the following cases of interrupts. When one of the serviced interrupts occurs, this bit is set to logical 1 by the hardware. This bit must be reset to logical 0 to re-enable the interrupts. (a) dmaEn = 1: During DMA, this bit is set to logical 1 when terminal count is reached. (b) dmaEn = 0, direction = 0: This bit is set to logical 1 whenever there are writeIntr threshold or more bytes free in the FIFO. (c) dmaEn = 0, direction = 1: This bit is set to logical 1 whenever there are readIntr threshold or more valid bytes to be read from the FIFO. Bit 1: Read only 0 The FIFO has at least one free byte. 1 The FIFO is completely full; it cannot accept another byte. Bit 0: Read only 0 The FIFO contains at least one byte of data. 1 The FIFO is completely empty.
12.3.11 ECP Pin Descriptions
NAME TYPE DESCRIPTION
NStrobe (HostClk) PD<7:0> nAck (PeriphClk)
O I/O I
This pin loads data or address into the slave on its asserting edge during write operations. This signal handshakes with Busy. These signals contain address, data or RLE data. This signal indicates valid data driven by the peripheral when asserted. This signal handshakes with nAutoFd in reverse. This signal deasserts to indicate that the peripheral can accept data. In the reverse direction, it indicates whether the data lines contain ECP command information or data. Normal data are transferred when Busy (PeriphAck) is high, and an 8-bit command is transferred when it is low. This signal is used to acknowledge a change in the direction of the transfer (asserted = forward). The peripheral drives this signal low to acknowledge nReverseRequest. The host relies upon nAckReverse to determine when it is permitted to drive the data bus. Indicates printer on-line.
Busy (PeriphAck)
I
PError (nAckReverse)
I
Select (Xflag)
I
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ECP Pin Descriptions , continued.
NAME
TYPE
DESCRIPTION
NautoFd (HostAck)
O
Requests a byte of data from the peripheral when it is asserted. In the forward direction, this signal indicates whether the data lines contain ECP address or data. Normal data are transferred when nAutoFd (HostAck) is high, and an 8-bit command is transferred when it is low. Generates an error interrupt when it is asserted. This signal is valid only in the forward direction. The peripheral is permitted (but not required) to drive this pin low to request a reverse transfer during ECP mode. This signal sets the transfer direction (asserted = reverse, deasserted = forward). This pin is driven low to place the channel in the reverse direction. This signal is always deasserted in ECP mode.
nFault (nPeriphReuqest) nInit (nReverseRequest) nSelectIn (ECPMode)
I
O O
12.3.12 ECP Operation
The host must negotiate on the parallel port to determine if the peripheral supports the ECP protocol before ECP operation. After negotiation, it is necessary to initialize some of the port bits. (a) Set direction = 0, enabling the drivers. (b) Set strobe = 0, causing the nStrobe signal to default to the deasserted state. (c) Set autoFd = 0, causing the nAutoFd signal to default to the deasserted state. (d) Set mode = 011 (ECP Mode) ECP address/RLE bytes or data bytes may be sent automatically by writing the ecpAFifo or ecpDFifo, respectively. 12.3.12.1. Mode Switching The software must handle P1284 negotiation and all operations prior to a data transfer in SPP or PS/2 modes (000 or 001). The hardware provides an automatic control line handshake, moving data between the FIFO and the ECP port, only in the data transfer phase (mode 011 or 010). If the port is in mode 000 or 001, it may switch to any other mode. If the port is not in mode 000 or 001, it can only be switched into mode 000 or 001. The direction can only be changed in mode 001. In extended forward mode, the software should wait for the FIFO to be empty before switching back to mode 000 or 001. In ECP reverse mode, the software should wait for all the data to be read from the FIFO before changing back to mode 000 or 001. 12.3.12.2. Command/Data ECP mode allows the transfer of normal 8-bit data or 8-bit commands. In the forward direction, normal data are transferred when HostAck is high, and an 8-bit command is transferred when HostAck is low. The most significant bits of the command indicate whether it is a run-length count (for compression) or a channel address. In the reverse direction, normal data are transferred when PeriphAck is high, and an 8-bit command is transferred when PeriphAck is low. The most significant bit of the command is always zero.
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12.3.12.3. Data Compression The W83627DHG hardware supports RLE decompression and can transfer compressed data to a peripheral. Odd (RLE) compression is not supported in the hardware, however. In order to transfer data in ECP mode, the compression count is written to ecpAFifo and the data byte is written to ecpDFifo.
12.3.13 FIFO Operation
The FIFO threshold is set in LD0 CRO0, bit 6 ~ 3. All data transferred to or from the parallel port can proceed in DMA or Programmed I/O (non-DMA) mode, as indicated by the selected mode. The FIFO is used in Parallel Port FIFO mode or ECP Parallel Port Mode. After a reset, the FIFO is disabled.
12.3.14 DMA Transfers
DMA transfers are always to or from the ecpDFifo, tFifo, or CFifo. DMA uses the standard PC DMA services. The ECP requests DMA transfers from the host by activating the PDRQ pin. The DMA empties or fills the FIFO using the appropriate direction and mode. When the terminal count in the DMA controller is reached, an interrupt is generated, and serviceIntr is asserted, which will disable the DMA.
12.3.15 Programmed I/O (NON-DMA) Mode
The ECP and parallel port FIFOs can also be operated using interrupt-driven, programmed I/O. Programmed I/O transfers are 1. To the ecpDFifo at 400h and ecpAFifo at 000h 2. From the ecpDFifo located at 400h 3. To / from the tFifo at 400h. The host must set dmaEn and serviceIntr to 0 and also must set the direction and state accordingly in the programmed I/O transfers. The ECP requests programmed I/O transfers from the host by activating the IRQ pin. The programmed I/O empties or fills the FIFO using the appropriate direction and mode.
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13. KEYBOARD CONTROLLER
The W83627DHG KBC (8042 with licensed KB BIOS) circuit is designed to provide the functions needed to interface a CPU with a keyboard and/or a PS/2 mouse and can be used with IBM(R)-compatible personal computers or PS/2-based systems. The controller receives serial data from the keyboard or PS/2 mouse, checks the parity of the data, and presents the data to the system as a byte of data in its output buffer. Then, the controller asserts an interrupt to the system when data are placed in its output buffer. The keyboard and PS/2 mouse are required to acknowledge all data transmissions. No transmission should be sent to the keyboard or PS/2 mouse until an acknowledgement is received for the previous data byte.
P24 P25 P21 KINH P17 P20 P27
KIRQ MIRQ GATEA20 KBRST KDAT KCLK
8042
GP I/O PINS Multiplex I/O PINS
P10 P26 T0
P12~P16
P23 T1 P22 P11
MCLK
MDAT
Keyboard and Mouse Interface
13.1 Output Buffer
The output buffer is an 8-bit, read-only register at I/O address 60h (Default, PnP programmable I/O address LD5-CR60 and LD5-CR61). The keyboard controller uses the output buffer to send the scan code (from the keyboard) and required command bytes to the system. The output buffer can only be read when the output buffer full bit in the register (in the status register) is logical 1.
13.2 Input Buffer
The input buffer is an 8-bit, write-only register at I/O address 60h or 64h (Default, PnP programmable I/O address LD5-CR60, LD5-CR61, LD5-CR62, and LD5-CR63). Writing to address 60h sets a flag to indicate a data write; writing to address 64h sets a flag to indicate a command write. Data written to I/O address 60h is sent to the keyboard (unless the keyboard controller is expecting a data byte) through the controller's input buffer only if the input buffer full bit (in the status register) is logical 0.
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13.3 Status Register
The status register is an 8-bit, read-only register at I/O address 64h (Default, PnP programmable I/O address LD5-CR62 and LD5-CR63) that holds information about the status of the keyboard controller and interface. It may be read at any time.
BIT BIT FUNCTION DESCRIPTION
0 1 2 3 4 5 6 7
Output Buffer Full Input Buffer Full System Flag Command/Data Inhibit Switch Auxiliary Device Output Buffer General Purpose Time-out Parity Error
0: Output buffer empty 1: Output buffer full 0: Input buffer empty 1: Input buffer full This bit may be set to 0 or 1 by writing to the system flag bit in the command byte of the keyboard controller. It defaults to 0 after a power-on reset. 0: Data byte 1: Command byte 0: Keyboard is inhibited 1: Keyboard is not inhibited 0: Auxiliary device output buffer empty 1: Auxiliary device output buffer full 0: No time-out error 1: Time-out error 0: Odd parity 1: Even parity (error)
13.4 Commands
COMMAND FUNCTION
20h 60h
Read Command Byte of Keyboard Controller Write Command Byte of Keyboard Controller
BIT 7 6 5 4 3 2 1 0 Reserved IBM Keyboard Translate Mode Disable Auxiliary Device Disable Keyboard Reserve System Flag Enable Auxiliary Interrupt Enable Keyboard Interrupt BIT DEFINITION
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Commands, continued
COMMAND
FUNCTION
A4h
A5h A6h A7h A8h A9h
Test Password Returns 0Fah if Password is loaded Returns 0F1h if Password is not loaded Load Password Load Password until a logical 0 is received from the system Enable Password Enable the checking of keystrokes for a match with the password Disable Auxiliary Device Interface Enable Auxiliary Device Interface Interface Test
BIT 00 01 02 03 04 BIT DEFINITION No Error Detected Auxiliary Device "Clock" line is stuck low Auxiliary Device "Clock" line is stuck high Auxiliary Device "Data" line is stuck low Auxiliary Device "Data" line is stuck low
AAh ABh
Self-test Returns 055h if self-test succeeds Interface Test
BIT 00 01 02 03 04 BIT DEFINITION No Error Detected Keyboard "Clock" line is stuck low Keyboard "Clock" line is stuck high Keyboard "Data" line is stuck low Keyboard "Data" line is stuck high
ADh AEh C0h C1h C2h D0h D1h D2h D3h D4h E0h FXh
Disable Keyboard Interface Enable Keyboard Interface Read Input Port (P1) and send data to the system Continuously puts the lower four bits of Port1 into the STATUS register Continuously puts the upper four bits of Port1 into the STATUS register Send Port 2 value to the system Only set / reset GateA20 line based on system data bit 1 Send data back to the system as if it came from the Keyboard Send data back to the system as if it came from Auxiliary Device Output next received byte of data from system to Auxiliary Device Reports the status of the test inputs Pulse only RC (the reset line) low for 6s if the Command byte is even
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13.5 Hardware GATEA20/Keyboard Reset Control Logic
The KBC includes hardware control logic to speed-up GATEA20 and KBRESET. This control logic is controlled by LD5-CRF0 as follows:
13.5.1 KB Control Register
BIT NAME 7 6 5 4 3 2 1 0
KCLKS1
KCLKS0 Reserved Reserved Reserved
P92EN
HGA20
HKBRST
KCLKS1, KCLKS0 These two bits select the KBC clock rate. 00: KBC clock input is 6 MHz 01: KBC clock input is 8 MHz 10: KBC clock input is 12 MHz 11: KBC clock input is 16 MHz P92EN (Port 92 Enable) 1: Enables Port 92 to control GATEA20 and KBRESET. 0: Disables Port 92 functions. HGA20 (Hardware GATEA20) 1: Selects hardware GATEA20 control logic to control GATE A20 signal. 0: Disables hardware GATEA20 control logic function. HKBRST (Hardware Keyboard Reset) 1: Selects hardware KB RESET control logic to control KBRESET signal. 0: Disables hardware KB RESET control logic function. When the KBC receives data that follows a "D1" command, the hardware control logic sets or clears GATEA20 according to received data bit 1. Similarly, the hardware control logic sets or clears KBRESET depending on received data bit 0. When the KBC receives an "FE" command, the KBRESET is pulse low for 6s (Min.) with a 14s (Min.) delay. GATEA20 and KBRESET are controlled by either software or hardware logic, and they are mutually exclusive. Then, GATEA20 and KBRESET are merged with Port92 when the P92EN bit is set.
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13.5.2 Port 92 Control Register
BIT NAME 7 6 5 4 3 2 1 0
Res. (0)
Res. (0)
Res. (1)
Res. (0)
Res. (0)
Res. (1)
SGA20
PLKBRST
SGA20 (Special GATE A20 Control) 1: Drives GATE A20 signal to high. 0: Drives GATE A20 signal to low. PLKBRST (Pull-Low KBRESET) A logical 1 on this bit causes KBRESET to drive low for 6 S(Min.) with a 14 S(Min.) delay. Before issuing another keyboard-reset command, the bit must be cleared.
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14. POWER MANAGEMENT EVENT
The PME# (pin 86) signal is connected to the South Bridge and is used to wake up the system from S1 ~ S5 sleeping states. One control bit and four registers in the W83627DHG are associated with the PME function. The control bit is at Logical Device A, CR[F2h], bit[0] and is for enabling or disabling the PME function. If this bit is set to "0", the W83627DHG won't output any PME signal when any of the wake-up events has occurred and is enabled. The four registers are divided into PME status registers and PME interrupt registers of wake-up events Note.1. 1) The PME status registers of wake-up event: - At Logical Device A, CR[F3h] and CR[F4h] - Each wake-up event has its own status - The PME status should be cleared by writing a "1" before enabling its corresponding bit in the PME interrupt registers 2) The PME interrupt registers of wake-up event: - At Logical Device A, CR[F6h] and CR[F7h] - Each wake-up event can be enabled / disabled individually to generate a PME# signal
Note.1
PME wake-up events that the W83627DHG supports include: Mouse IRQ event Keyboard IRQ event Printer IRQ event Floppy IRQ event UART A IRQ event UART B IRQ event Hardware Monitor IRQ event WDTO# event RIB (UARTB Ring Indicator) event
14.1 Power Control Logic
This chapter describes how the W83627DHG implements its ACPI function via these power control pins: PSIN# (Pin 68), PSOUT# (Pin 67), SUSB# (i.e. SLP_S3#; Pin 73) and PSON# (Pin 72). The following figure illustrates the relationships.
PSON#
3VCC 3VSB/VBAT
PSIN# W83627DHG
IOCLK 48 / 24 MHz
PSOUT#
PWRBTN#
PSON#
South Bridge
SLP_S3#
Power Supply
VCC ON
SUSB#
Figure 14.1
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14.1.1 PSON# Logic
14.1.1.1. Normal Operation The PSOUT# signal will be asserted low if the PSIN# signal is asserted low. The PSOUT# signal is held low for as long as the PSIN# is held low. The South Bridge controls the SUSB# signal through the PSOUT# signal. The PSON# is directly connected to the power supply to turn on or off the power. Figure 14.2 shows the power on and off sequences. The ACPI state changes from S5 to S0, then to S5
PSON# SUSB# (Intel Chipset) SUSB# (Other Chipset) PSOUT# PSIN# 3VSB S5 State
Figure 14.2
S0 State
S5 State
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14.1.2 AC Power Failure Resume By definition, AC power failure means that the standby power is removed. The power failure resume control logic of the W83627DHG is used to recover the system to a pre-defined state after AC power failure. Two control bits at Logical Device A, CR[E4h], bits[6:5] indicate the pre-defined state. The definition of these two bits is listed in the following table:
LOGICAL DEVICE A, CR[E4H], BITS[6:5]
DEFINITION
00 01 10 11
System always turns off when it returns from AC power failure System always turns on when it returns from AC power failure System turns off / on when it returns from power failure depending on the state before the power failure. (Please see Note 1) User defines the state before the power failure. (The previous state is set at CRE6[4]. Please see Note 2)
Note1. The W83627DHG detects the state before power failure (on or off) through the SUSB# signal and the 3VCC power. The relation is illustrated in the following two figures.
3VCC SUSB#
Figure 14.3 The previous state is "on" - 3VCC falls to 2.6V and SUSB# keeps at 2.0V
3VCC SUSB#
Figure 14.4 The previous state is "off" - 3VCC falls to 2.6V and SUSB# keeps at 0.8V Note 2.
LOGICAL DEVICE A, CR[E6H] BIT [4]
0 1
DEFINITION
User defines the state to be "on" User defines the state to be "off"
To ensure that VCC does not fall faster than VSB in various ATX Power Supplies, the W83627DHG adds the option of "user define mode" for the pre-defined state before AC power failure. BIOS can set the pre-defined state
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to be "On" or "Off". According to this setting, the system is returned to the pre-defined state after the AC power recovery.
14.2 Wake Up the System by Keyboard and Mouse
The W83627DHG generates a low pulse through the PSOUT# pin to wake up the system when it detects a key code pressed or mouse button clicked. The following sections describe how the W83627DHG works.
14.2.1 Waken up by Keyboard events The keyboard Wake-Up function is enabled by setting Logical Device A, CR[E0h], bit 6 to "1". There are two keyboard events can be used for the wake-up 1) Any key - Set bit 0 at Logical Device A, CR[E0h] to "1" (Default). 2) Specific keys (Password) - Set bit 0 at Logical Device A, CR[E0h] to "0". Three sets of specific key combinations are stored at Logical Device A. CR[E1h] is an index register to indicate which byte of key code storage (0x00h ~ 0x0Eh, 0x30h ~ 0x3Eh, 0x40h ~ 0x4Eh) is going to be read or written through CR[E2h]. According to IBM 101/102 keyboard specification, a complete key code contains a 1-byte make code and a 2-byte break code. For example, the make code of "0" is 0x45h, and the corresponding break code is 0xF0h, 0x45h. The approach to implement Keyboard Password Wake-Up Function is to fill key codes into the password storage. Assume that we want to set "012" as the password. The storage should be filled as below. Please note that index 0x09h ~ 0x0Eh must be filled as 0x00h since the password has only three numbers.
Index(CRE1) D a t a (CRE2) 00 1E 01 F0 02 1E 03 16 04 F0 05 16 06 45 07 F0 08 45 09 00 0A 00 0B 00 0C 0D 00 00 0E 00
First-pressed key "0" Second-pressed key "1" Third-pressed key "2"
14.2.2 Waken up by Mouse events The mouse Wake-Up function is enabled by setting Logical Device A, CR[E0h], bit 5 to "1". The following specific mouse events can be used for the wake-up: Any button clicked or any movement One click of the left or the right button One click of the left button One click of the right button Two clicks of the left button Two clicks of the right button.
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Three control bits (ENMDAT_UP, MSRKEY, MSXKEY) define the combinations of the mouse wake-up events. Please see the following table for the details. Table 14.1
ENMDAT_UP (LOGICAL DEVICE A, CR[E6H], BIT 7) MSRKEY (LOGICAL DEVICE A, CR[E0H], BIT 4) MSXKEY (LOGICAL DEVICE A, CR[E0H], BIT 1) WAKE-UP EVENT
1 1 0 0 0 0
x x 0 1 0 1
1 0 1 1 0 0
Any button clicked or any movement. One click of the left or right button. One click of the left button. One click of the right button. Two clicks of the left button. Two clicks of the right button.
14.3 Resume Reset Logic
The RSMRST# (Pin 75) signal is a reset output and is used as the 3VSB power-on reset signal for the South Bridge. When the W83627DHG detects the 3VSB voltage rises to "V1", it then starts a delay - "t1" before the rising edge of RSMRST# asserting. If the 3VSB voltage falls below "V2", the RSMRST# de-asserts immediately. Timing and voltage parameters are shown in Figure 14.5 and Table 14.2.
t1 RSMRST#
3VSB
V1
Figure 14.5
V2
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SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
NOTE
V1 V2 V1 V2 t1
3VSB Valid Voltage 3VSB Ineffective Voltage 3VSB Valid Voltage 3VSB Ineffective Voltage Valid 3VSB to RSMRST# inactive
2.4 2.25 2.4 100
2.6 2.4 -
2.75 2.55 3.1 200
V V V V mS
For both UBC and UBE version For both UBC and UBE version For UBF version For UBF version
Table 14.2
14.4 PWROK Generation
The PWROK (Pin 71) signal is an output and is used as the 3VCC power-on reset signal. When the W83627DHG detects the 3VCC voltage rises to "V3", it then starts a delay - "t2" before the rising edge of PWROK asserting. If the 3VCC voltage falls below "V4", the PWROK de-asserts immediately. Timing and voltage parameters are shown in Figure 14.6 and Table 14.3.
t2 PWROK
3VCC
V3
Figure 14.6
V4
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
NOTE
V3 V4 V3 V4 t2
3VCC Valid Voltage 3VCC Ineffective Voltage 3VCC Valid Voltage 3VCC Ineffective Voltage Valid 3VCC to PWROK active
2.4 2.25 2.4 300
2.6 2.4 -
2.75 2.55 3.1 500
V V V V mS
For both UBC and UBE version For both UBC and UBE version For UBF version For UBF version
Table 14.3 Originally, the t2 timing is between 300 mS to 500 mS, but it can be changed to 200 mS to 300 mS by programming Logical Device A, CR[E6h], bit 3 to "1". Furthermore, the W83627DHG provides four different extra delay time of PWROK for various demands. The four extra delay time are designed at Publication Release Date: Aug, 22, 2007 Version 1.4
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Logical Device A, CR[E6h], bits 2~1. The following table shows the definitions of Logical Device A, CR[E6h] bits 3 ~1.
LOGICAL DEVICE A, CR[E6H] BIT DEFINITION
3
PWROK_DEL (first stage) (VSB) Set the delay time when rising from PWROK_LP to PWROK_ST. 0: 300 ~ 500 mS. 1: 200 ~ 300 mS. PWROK_DEL (VSB) Set the delay time when rising from PWROK_ST to PWROK. 00: No delay time. 01: Delay 32 mS 10: 96 mS 11: Delay 250 mS
2~1
For example, if Logical Device A, CR[E6h] bit 2 is set to "0" and bits 2~1 are set to "10", the range of t2 timing is from 396(300 + 96) mS to 596(500 + 96) mS. * In UBE and UBF version, PWROK2 generation is the same as PWROK generation.
14.4.1 The Relation among PWROK/PWROK2, ATXPGD and FTPRST# - both for UBE and UBF Version Only PWROK and PWROK2 signals as well as ATXPGD and FTPRST# input signals are interrelated. Once the FTPRST# signal changes from high to low then to high, the PWROK and PWROK2 signals will have the same transition after 28mS ~ 39mS delay. The relation and parameter are illustrated in the
following figure and table.
FTPRST#
TL
t3 PWROK/PWROK2
TL
3VCC
Figure 14.7
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Table 14.4
SYMBOL PARAMETER MIN MAX UNIT
t3
FTPRST# active to PWROK active
28
39
mS
Note. 1. The values above are the worst-case results of R&D simulation 2. The length of TL level is based on the length of the low level of FTPRST# Additionally, the ATXPGD signal, too, is used to control the generation of PWROK and PWROK2. In Figure 14.8, the 3VCC voltage rises to "V3", and then starts a delay - "t2" for PWROK and PWROK2 generation. However, ATXPGD is still inactive after t2; therefore the delay time before the rising edge of PWROK and PWROK2 are t2 plus Td. The length of Td is based on when the ATXPGD signal is active. Once 3VCC falls below "V4" or the ATXPGD signal is inactive, PWROK and PWROK2 de-assert immediately.
PWROK/PWROK2 are active when both 3VCC and ATXPGD are valid 3VCC V3 V4
ATXPGD(input) t2 PWROK/PWROK2 (output)
Td
Figure 14.8
PWROK/PWROK2 are inactive when either 3VCC or ATXPGD is invalid
In Figure 14.9, the 3VCC voltage rises to "V3", and the ATXPGD is active during t2, so PWROK and PWROK2 assert after t2. The timing of t2 starts when 3VCC voltage rises to "V3". No matter the ATXPGD signal activation is during or after t2, PWROK and PWROK2 assert or de-assert according to the 3VCC voltage and the ATXPGD signal.
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3VCC
V3
Ta
V4
ATXPGD(input) t2 PWROK/PWROK2 (output)
PWROK/PWROK2 are active when both 3VCC and ATXPGD are valid
PWROK/PWROK2 are inactive even when 3VCC is valid
Figure 14.9
Timing and voltage parameters are shown in the following table.
SYMBOL PARAMETER MIN. TYP. MAX. UNIT NOTE
V3 V4 V3 V4 t2
3VCC Valid Voltage 3VCC Ineffective Voltage 3VCC Valid Voltage 3VCC Ineffective Voltage Starting from valid 3VCC
2.4 2.25 2.4 300
2.6 2.4 -
2.75 2.55 3.1 500
V V V V mS
For both UBC and UBE version For both UBC and UBE version For UBF version For UBF version
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15. SERIALIZED IRQ
The W83627DHG supports a serialized IRQ scheme. This allows a signal line to be used to report the parallel interrupt requests. Since more than one device may need to share the signal serial SERIRQ signal, an open drain signal scheme is employed. The clock source is the PCI clock. The serialized interrupt is transferred on the SERIRQ signal, one cycle consisting of three frames types: the Start Frame, the IRQ/Data Frame, and the Stop Frame.
15.1 Start Frame
There are two modes of operation for the SERIRQ Start Frame: Quiet mode and Continuous mode. In the Quiet mode, the W83627DHG drives the SERIRQ signal active low for one clock, and then tri-states it. This brings all the state machines of the W83627DHG from idle to active states. The host controller (the South Bridge) then takes over driving SERIRQ signal low in the next clock and continues driving the SERIRQ low for programmable 3 to 7 clock periods. This makes the total number of clocks low 4 to 8 clock periods. After these clocks, the host controller drives the SERIRQ high for one clock and then tri-states it. In the Continuous mode, the START Frame can only be initiated by the host controller to update the information of the IRQ/Data Frame. The host controller drives the SERIRQ signal low for 4 to 8 clock periods. Upon a reset, the SERIRQ signal is defaulted to the Continuous mode for the host controller to initiate the first Start Frame. Please see the diagram below for more details. Start Frame Timing with source sampled a low pulse on IRQ1.
SL
or
START FRAME H R T
IRQ0 FRAME S R T
IRQ1 FRAME S R T
SMI# FRAME S R T
H PCICLK SERIRQ Drive Source IRQ1
2
START 1 Host Controller None IRQ1 None
H=Host Control Note:
SL=Slave Control
R=Recovery
T=Turn-around
S=Sample
1. The Start Frame pulse can be 4-8 clocks wide. 2. The first clock of Start Frame is driven low by the W83627DHG because IRQ1 of the W83627DHG needs an interrupt request. Then the host takes over and continues to pull the SERIRQ low.
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15.2 IRQ/Data Frame
Once the Start Frame has been initiated, the W83627DHG must start counting frames based on the rising edge of the start pulse. Each IRQ/Data Frame has three clocks: the Sample phase, the Recovery phase, and the Turn-around phase. During the Sample phase, the W83627DHG drives SERIRQ low if the corresponding IRQ is active. If the corresponding IRQ is inactive, then SERIRQ must be left tri-stated. During the Recovery phase, the W83627DHG device drives the SERIRQ high. During the Turn-around phase, the W83627DHG device leaves the SERIRQ tri-stated. The W83627DHG starts to drive the SERIRQ line from the beginning of "IRQ0 FRAME" based on the rising edge of PCICLK.
The IRQ/Data Frame has a specific numeral order, as shown in Table 15.1. Table 15.1 SERIRQ Sampling Periods
SERIRQ SAMPLING PERIODS IRQ/DATA FRAME SIGNAL SAMPLED # OF CLOCKS PAST START EMPLOYED BY
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 32:22
IRQ0 IRQ1 SMI# IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IOCHCK# INTA# INTB# INTC# INTD# Unassigned
2 5 8 11 14 17 20 23 26 29 32 35 38 41 44 47 50 53 56 59 62 95
Keyboard UART B UART A FDC LPT Mouse -
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15.3 Stop Frame
After all IRQ/Data Frames have completed, the host controller will terminates SERIRQ with a Stop frame. Only the host controller can initiate the Stop Frame by driving SERIRQ low for 2 or 3 clocks. If the Stop Frame is low for 2 clocks, the Sample mode of next SERIRQ cycle's Sample mode is the Quiet mode. If the Stop Frame is low for 3 clocks, the Sample mode of next SERIRQ cycle is the Continuous mode. Please see the diagram below for more details. Stop Frame Timing with Host Using 17 SERIRQ sampling period.
IRQ14 FRAME S PCICLK SERIRQ Driver None R T S
IRQ15 FRAME R T
IOCHCK# FRAME S R T
STOP FRAME
NEXT CYCLE T
I1
H
R
STOP IRQ15 None Host Controller
START 2
H=Host Control Note:
R=Recovery
T=Turn-around
S=Sample
I= Idle.
1. There may be none, one or more Idle states during the Stop Frame. 2. The Start Frame pulse of next SERIRQ cycle may or may not start immediately after the turn-around clock of the Stop Frame.
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16. WATCHDOG TIMER
The WDTO# pin is a multi-function pin with GP50 functions and is configured to the WDTO# function, if Configuration Register CR[2Dh], bit 0 is set to zero. The Watchdog Timer of the W83627DHG consists of an 8-bit programmable time-out counter and a control and status register. The time-out counter ranges from 1 to 255 minutes in the minute mode, or 1 to 255 seconds in the second mode. The units of Watchdog Timer counter are selected at Logical Device 8, CR[F5h], bit[3]. The time-out value is set at Logical Device 8, CR[F6h]. Writing zero disables the Watchdog Timer function. Writing any non-zero value to this register causes the counter to load this value into the Watchdog Timer counter and start counting down. The W83627DHG outputs a low signal to the WDTO# pin (pin 77) when a time-out event occurs. In other words, when the value is counted down to zero, the timer stops, and the W83627DHG sets the WDTO# status bit in Logical Device 8, CR[F7h], bit[4], outputting a low signal to the WDTO# pin(pin 77). Writing a zero will clear the status bit and the WDTO# pin returns to high. Writing a zero will clear the status bit. This bit will also be cleared if LRESET# or PWROK# signal is asserted. Additionally, GP40 (pin 85), GP42 (pin 83), GP44 (pin 81) and GP46 (pin 79) provides an alternative WDTO# function. This function can be configured by the relative GPIO control register. Please note that the output type of WDTO# (pin 77) and GP42 (pin 83) is push-pull and that of GP40 (pin 85), GP44 (pin 81) and GP46 (pin 79) is open-drain.
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Publication Release Date: Aug, 22, 2007 Version 1.4
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17. GENERAL PURPOSE I/O
The W83627DHG provides 40 input/output ports that can be individually configured to perform a simple basic I/O function or alternative, pre-defined function. GPIO port 6 is configured through control registers in Logical Device 7, and GPIO ports 2 ~ 5 in Logical Device 9. Users can configure each individual port to be an input or output port by programming respective bit in selection register (0 = output, 1 = input). Invert port value by setting inversion register (0 = non -inverse, 1 = inverse). Port value is read / written through data register. In addition, only GP30, GP31 and GP35 are designed to be able to assert PSOUT# or PME# signal to wake up the system if any of them has any transitions. There are about 16mS debounced circuit inside these 3 GPIOs and it can be disabled by programming respective bit (LD9, CR[FEh] bit 4~6). Users can set what kind of event type, level or edge, and polarity, rising or falling, to perform the wake-up function. The following table gives a more detailed register map on GP30, GP31 and GP35.
EVENTROUTE I EVENTROUTE II EVENT DEBOUNCED (PSOUT#) (PME#) 0 : ENABLE 0: DISABLE 0: DISABLE 1 : DISABLE 1: ENABLE 1: ENABLE GP30 EVENT TYPE 0 : EDGE 1: LEVEL EVENT POLARITY 0 : RISING 1 : FALLING
EVENT STATUS
LDA, CR[FEh] bit4 LDA, CR[FEh] bit5 LDA, CR[FEh] bit6
LDA, CR[FEh] bit0 LDA, CR[FEh] bit1 LDA, CR[FEh] bit2
LD9, CR[FEh] bit4 LD9, CR[FEh] bit5 LD9, CR[FEh] bit6
LD9, CR[FEh] bit0 LD9, CR[FEh] bit1 LD9, CR[FEh] bit2
LD9, CR[F2h] bit0 LD9, CR[F2h] bit1 LD9, CR[F2h] bit5
LD9, CR[E7h] bit0 LD9, CR[E7h] bit1 LD9, CR[E7h] bit5
GP31
GP35
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18. VID INPUTS AND OUTPUTS
The W83627DHG provides eight pins for VID input or output function. The default function is VID input. These pins can be configured to VID output function by setting Logical Device B, CR[F0h], bit 7 to 0. The configuration is applied to the 8 pins as a group. None of them can be individually set to input or output.
18.1 VID Input Detection
The W83627DHG supports Intel VRM 9/10/11 and AMD VRM VID detections. H/W strapping and S/W programming can set the following three input levels. a) and b) can be set by H/W strapping or S/W programming, while c) can only be set by S/W programming. a) TTL (Vih = 2 V; Vil = 0.8V) - 1) Add a pulled-down resistor at Pin 77(EN_GTL), or 2) Set Configuration Register CR[2Ch], bit 3 to "0"; b) GTL (Vih = 0.6 V; Vil = 0.4 V) - (Default) 1) No extra pulled-up resistor needed, or 2) Set Configuration Register CR[2Ch], bit 3 to "1"; c) AMD VRM (Vih = 1.4V; Vil = 0.8V) - Set Configuration Register CR[2Ch], bit 3 to "1" and Logical Device B, CR[F0h], but 6 to "1". The input data can be read in the data register at Logical Device B, CR[F1h], bit 7 ~ 0. It is a read/write register where bit 7~0 corresponds to VID pin 7~0. Please note that in the input mode, writes to this register have no effect.
18.2 VID Output Control
The output type of the eight VID pins is push-pull, and they drive to 3VCC (3.3V) when configured to the output mode. The output data can be set in the data register (Logical Device B, CR[F1h], bit 7 ~ 0). The written data can be read if Configuration Register CR[2Ch], bit 3 is set to "0".
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19. PCI RESET BUFFERS
The W83627DHG has five copies of LRESET# output buffers. LRESET# is LPC Interface Reset, to which PCI Reset is connected. The five copies of LRESET# in the W83627DHG are designated RSTOUT0#, RSTOUT1#, RSTOUT2#, RSTOUT3# and RSTOUT4#. All of them are powered by a 3VSB power. RSTOUT0# is an open-drain output buffer of LRESET#. This signal needs an external pulled-up resistor of 3.3V or 5V. RSTOUT1#, RSTOUT2#, RSTOUT3# and RSTOUT4# are push-pull output buffers of LRESET#. Each of them outputs 3.3V, voltage and the state is low when the 3VSB power is the only power source.
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Publication Release Date: Aug, 22, 2007 Version 1.4
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20. CONFIGURATION REGISTER 20.1 Chip (Global) Control Register
CR 02h. (Software Reset; Write Only)
BIT READ / WRITE DESCRIPTION
7~1 0
Reserved. Write "1" Only Software RESET.
CR 07h. (Logical Device; Default 00h)
BIT READ / WRITE DESCRIPTION
7~0
R/W
Logical Device Number.
CR 20h. (Chip ID, High Byte; Read Only)
BIT READ / WRITE DESCRIPTION
7~0
Read Only
Chip ID number = A0h (high byte).
CR 21h. (Chip ID, Low Byte; Read Only)
BIT READ / WRITE DESCRIPTION
7~0
Read Only
Chip ID number = 2Xh (low byte). X is the IC version
CR 22h. (Device Power Down; Default FFh)
BIT READ / WRITE DESCRIPTION
7 6 5 4 3 2~1 0
Reserved. R/W R/W R/W R/W Reserved. R/W FDC Power Down. 0: Powered down. 1: Not powered down. HM Power Down. 0: Powered down. 1: Not powered down. 0: Powered down. 1: Not powered down. 0: Powered down. 1: Not powered down. UARTB Power Down. UARTA Power Down. PRT Power Down.
0: Powered down. 1: Not powered down.
CR 23h. (IPD; Default 00h)
BIT READ / WRITE DESCRIPTION
7~1 0
Reserved. R/W IPD (Immediate Power Down). When set to 1, the whole chip is put into power-down mode immediately.
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W83627DHG
CR 24h. (Global Option; Default 0100_0ss0b)
BIT READ / WRITE
s: value by strapping
DESCRIPTION
7
R/W
Select output type of CPUFANOUT1 =0 CPUFANOUT1 is Push-pull. (Default) =1 CPUFANOUT1 is Open-drain. CLKSEL => Input clock rate selection = 0 The clock input on pin 18 is 24 MHz. = 1 The clock input on pin 18 is 48 MHz. (Default) Select output type of AUXFANOUT =0 AUXFANOUT is Push-pull. (Default) =1 AUXFANOUT is Open-drain. Select output type of SYSFANOUT =0 SYSFANOUT is Open-drain. (Default) =1 SYSFANOUT is Push-pull. Select output type of CPUFANOUT0 =0 CPUFANOUT0 is Open-drain. (Default) =1 CPUFANOUT0 is Push-pull. ENKBC => Enable keyboard controller = 0 KBC is disabled after hardware reset. = 1 KBC is enabled after hardware reset. This bit is read-only, and it is set or reset by a power-on strapping pin (Pin 54, SOUTA). ENROM => Enable Serial Peripheral Interface = 0 ROM is disabled after hardware reset. = 1 ROM is enabled after hardware reset. This bit is set or reset by a power-on strapping pin (Pin 52, DTRA#).
Note 1
6
R/W
5
R/W
4
R/W
3
R/W
2
Read Only
1
R/W
0 Note1:
Reserved.
Disable Serial Peripheral Interface Pin 2 Pin 19 Pin 58 GP23 GP22 AUXFANIN1
Enable Serial Peripheral Interface Pin 2 Pin 19 Pin 58 SCK SCE SI
Pin 118 BEEP
Pin 118 SO
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
CR 25h. (Interface Tri-state Enable; Default 00h)
BIT READ / WRITE DESCRIPTION
7~6 5 4 3 2~1 0
Reserved. R/W R/W R/W Reserved. R/W FDCTRI. s: value by strapping
DESCRIPTION
UARTBTRI UARTATRI PRTTRI
CR 26h. (Global Option; Default 0s000000b)
BIT READ / WRITE
7 6
Reserved. R/W HEFRAS => = 0 Write 87h to location 2E twice. = 1 Write 87h to location 4E twice. The corresponding power-on strapping pin is RTSA# (Pin 51). LOCKREG => = 0 Enable R/W configuration registers. = 1 Disable R/W configuration registers. DSFDLGRQ => = 0 Enable FDC legacy mode for IRQ and DRQ selection. Then DO register (base address + 2) bit 3 is effective when selecting IRQ. = 1 Disable FDC legacy mode for IRQ and DRQ selection. Then DO register (base address + 2) bit 3 is not effective when selecting IRQ. DSPRLGRQ => = 0 Enable PRT legacy mode for IRQ and DRQ selection. Then DCR register (base address + 2) bit 4 is effective when selecting IRQ. = 1 Disable PRT legacy mode for IRQ and DRQ selection. Then DCR register (base address + 2) bit 4 is not effective when selecting IRQ. DSUALGRQ => = 0 Enable UART A legacy mode for IRQ selection. Then HCR register (base address + 4) bit 3 is effective when selecting IRQ. = 1 Disable UART A legacy mode for IRQ selection. Then HCR register (base address + 4) bit 3 is not effective when selecting IRQ. DSUBLGRQ => = 0 Enable UART B legacy mode for IRQ selection. Then HCR register (base address + 4) bit 3 is effective when selecting IRQ. = 1 Disable UART B legacy mode for IRQ selection. Then HCR register (base address + 4) bit 3 is not effective when selecting IRQ.
5 4
R/W Reserved.
3
R/W
2
R/W
1
R/W
0
R/W
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CR 27h. (Reserved) CR 28h. (Global Option; Default 50h)
BIT READ / WRITE DESCRIPTION
7
Reserved. Flash ROM size select = 00 1M = 01 2M = 10 4M (Default) = 11 8M Select to enable/disable decoding of BIOS ROM range 000E xxxxh. =0 Enable decoding of BIOS ROM range at 000E xxxxh. =1 Disable decoding of BIOS ROM range at 000E xxxxh. Select to enable/disable decoding of BIOS ROM range FFE xxxxx. =0 Enable decoding of BIOS ROM range at FFE xxxxx. =1 Disable decoding of BIOS ROM range at FFE xxxxx. PRTMODS2 ~ 0 => = 0xx Parallel Port Mode. = 1xx Reserved.
6~5
R/W
4
R/W
3
R/W
2~0
R/W
CR 29h. (Multi-function Pin Selection; Default 00h)
BIT READ / WRITE DESCRIPTION
7 6 5~4 3
Reserved. R/W Reserved. R/W Pins 49 ~ 54, 56 ~ 57 function select = 0 Pins 49 ~ 54, 56 ~ 57 UART A = 1 Pins 49 ~ 54, 56 ~ 57 GPIO6 Pin 119 ~ 120 function select Bit-2 Bit-1 0 1 Pin 119 ~ 120 function Pin 119 ~ 120 CPUFANIN1, CPUFANOUT1 (Default) Pin 119 ~ 120 GP21, GP20 Pin 5 function select =0 OVT# =1 SMI#
2~1
R/W
0 0
0
Reserved.
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CR 2Ah. (SPI Configuration; Default 00h) (VSB Power)
BIT READ / WRITE DESCRIPTION
7~6
R/W
Serial Peripheral Interface Configuration bit. (VSB) - These two bits are for UBE and UBF version only = 00 Normal read. SPI clock is 16MHz. = 01 Normal read. SPI clock is 33MHz. = 10 Normal read. SPI clock is 22MHz. = 11 Reserved. Note: These two bits are ignored when CR24, bit 1 is "0" (SPI function is disabled). Serial Peripheral Interface configuration bit.(VBAT) = 00 Normal read. The clock rate is based on the setting of CR[2Ah], bits[7:6] = 01 Reserved = 10 Reserved = 11 Fast read with one dummy byte. The clock rate is 33MHz. If set to "11", CR[2Ah], bits[7:6] must be 0.
Note: These two bits are ignored when CR24, bit 1 is "0". (SPI function is disabled)
5~4
R/W
3
R/W
SDA_filter_EN: 0: Enable SDA input to a filter 1: Disable SDA input to a filter SCL_filter_EN: 0: Enable SCL input to a filter 1: Disable SCL input to a filter Pin 89, Pin 90 function select (I2C interface) = 0 {Pin 89, Pin 90} set by CR2C bits[6:5]. = 1 {Pin 89, Pin 90} SDA, SCL. KB, MS pin function select = 0 KB, MS function. = 1 GPIO function.(GP24, GP25, GP26 and GP27)
2
R/W
1
R/W
0
R/W
* Normal Read: Read 1-byte data. Fast Read: Read 4-byte data. CR 2Bh. (Reserved)
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Publication Release Date: Aug, 22, 2007 Version 1.4
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CR 2Ch. (Multi-function Pin Selection; Default E2h) (VSB Power)
BIT READ / WRITE DESCRIPTION
7
R/W
Pin 88 Select = 0 GP34 = 1 RSTOUT4# (Default) Pin 89 Select = 0 GP33 = 1 RSTOUT3# (Default)
Note: This bit is ignored when CR2A, bit 1 is High.
6
R/W
5
R/W
Pin 90 Select = 0 GP32 = 1 RSTOUT2# (Default)
Note: This bit is ignored when CR2A, bit 1 is High.
4
Read Only
EN_ACPI status bit = 0 Particular ACPI functions are disabled. = 1 Particular ACPI functions are enabled. The bit is strapped by Pin 70 (GP55). While particular ACPI functions are enabled (EN_ACPI = 1), GPIO3 pins (pins 64, 69, 87, 91 and 92) are disabled and the particular ACPI functions are activated (SUSC#, FTPRST#, ATXPGD, VSBGATE# and PWROK2) * This bit is available both for UBE and UBF version EN_GTL Configure bit = 0 VID input voltage is TTL. = 1 VID input voltage is GTL. The bit is strapped by Pin 77 (GP50).--- Internal Pull high to 3VSB. EN_PWRDN. (VBAT) = 0 Thermal shutdown function is disabled. = 1 Enable thermal shutdown function. Pins 78 ~ 85 function select Bit-1 0 Bit-0 0 Pins 78 ~ 85 function Pin 82 Reserved (tri-state) Pin 83 Reserved (always low) Others GPIO4 Pin 82 IRRX Pin 83 IRTX Others GPIO4 Pins 78 ~ 85 GPIO4 Pins 78 ~ 85 UART B
3
R/W
2
R/W
1~0
R/W 0 1 1 1 0 1
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CR 2Dh. (Multi-function Pin Selection; default 21h) (VSB Power)
BIT READ / WRITE DESCRIPTION
7
R/W
Pin 67 Select (reset by RSMRST#) = 0 PSOUT# = 1 GPIO57 Pin 68 Select (reset by RSMRST#) = 0 PSIN# = 1 GPIO56 Pin 70 Select (reset by RSMRST#) = 0 SUSLED = 1 GPIO55 Pin 71 Select (reset by RSMRST#) = 0 PWROK = 1 GPIO54 Pin 72 Select (reset by RSMRST#) = 0 PSON# = 1 GPIO53 Pin 73 Select (reset by RSMRST#) = 0 SUSB# = 1 GPIO52 Pin 75 Select (reset by RSMRST#) = 0 RSMRST# = 1 GPIO51 Pin 77 Select (reset by RSMRST#) = 0 WDTO# = 1 GPIO50
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
R/W
CR 2Eh. (Default 00h)
BIT READ / WRITE DESCRIPTION
7~0
R/W
Test Mode Bits: Reserved for Winbond.
CR 2Fh. (Default 00h)
BIT READ / WRITE DESCRIPTION
7~0
R/W
Test Mode Bits: Reserved for Winbond.
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20.2 Logical Device 0 (FDC)
CR 30h. (Default 01h)
BIT READ / WRITE DESCRIPTION
7~1 0
Reserved. R/W 0: Logical device is inactive. 1: Activate the logical device.
CR 60h, 61h. (Default 03h,F0h)
BIT READ / WRITE DESCRIPTION
7~0
R/W
These two registers select FDC I/O base address <100h: FF8h> on 8 bytes boundary.
CR 70h. (Default 06h)
BIT READ / WRITE DESCRIPTION
7~4 3~0
Reserved. R/W These bits select IRQ resource for FDC.
CR 74h. (Default 02h)
BIT READ / WRITE DESCRIPTION
7~3 2~0
Reserved. R/W These bits select DRQ resource for FDC. 000: DMA0. 001: DMA1. 010: DMA2. 1xx: No DMA active. 011: DMA3.
CR F0h. (Default 8Eh)
BIT READ / WRITE DESCRIPTION
7 6
Reserved. R/W This bit determines the polarity of all FDD interface signals. 0: FDD interface signals are active low. 1: FDD interface signals are active high. When this bit is logic 0, indicates a second drive is installed and is reflected in status register A. (PS2 mode only) Swap Drive 0, 1 Mode => 0: No Swap. 1: Drive and Motor select 0 and 1 are swapped. Interface Mode. 00: Model 30. 10: Reserved. 01: PS/2. 11: AT Mode
5 4 3~2
R/W R/W R/W
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Continued
BIT
READ / WRITE
DESCRIPTION
1 0
R/W R/W
FDC DMA Mode. Floppy Mode.
0: Burst Mode is enabled 1: Non-Burst Mode. 0: Normal Floppy Mode. 1: Enhanced 3-mode FDD.
CR F1h. (Default 00h)
BIT READ / WRITE DESCRIPTION
7~6 5~4 3~2
R/W R/W R/W
Boot Floppy.
00: FDD A. 10: Reserved.
01: Reserved. 11: Reserved.
Media ID1, Media ID0. These bits will be reflected on FDC's Tape Drive Register bit 7, 6. Density Select. 00: Normal. 10: 1 (Forced to logic 1). 01: Normal. 11: 0 (Forced to logic 0).
1
R/W
DISFDDWR => 0: Enable FDD write. 1: Disable FDD write (forces pins WE, WD to stay high). SWWP => 0: Normal, use WP to determine whether the FDD is write protected or not. 1: FDD is always write-protected.
0
R/W
CR F2h. (Default FFh)
BIT READ / WRITE DESCRIPTION
7~2 1~0
Reserved. R/W FDD A Drive Type.
CR F4h. (Default 00h)
BIT READ / WRITE DESCRIPTION
7 6 5 4~3 2 1~0
Reserved. R/W Reserved. R/W Reserved. R/W Drive Type selection (Refer to TABLE B). Data Rate Table selection (Refer to TABLE A). 00: Select regular drives and 2.88 format. 01: 3-mode drive. 10: 2 Meg Tape. 11: Reserved. 0: Enable FDC Pre-compensation. 1: Disable FDC Pre-compensation.
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CR F5h. (Default 00h)
BIT READ / WRITE DESCRIPTION
7~0
R/W
Same as FDD0 of CR F5h.
TABLE A
DRIVE RATE TABLE SELECT DRTS1 DRTS0 DATA RATE DRATE1 DRATE0 SELECTED DATA RATE MFM FM SELDEN
1 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 0 1
1 0 1 0 1 0 1 0 1 0 1 0
1Meg 500K 300K 250K 1Meg 500K 500K 250K 1Meg 500K 2Meg 250K
--250K 150K 125K --250K 250K 125K --250K --125K
1 1 0 0 1 1 0 0 1 1 0 0
TABLE B DTYPE0 DTYPE1 DRVDEN0 (pin 2) DRIVE TYPE 4/2/1 MB 3.5"" 0 0 SELDEN 2/1 MB 5.25" 2/1.6/1 MB 3.5" (3-MODE) 0 1 1 1 0 1 DRATE1
SELDEN
DRATE0
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Publication Release Date: Aug, 22, 2007 Version 1.4
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20.3 Logical Device 1 (Parallel Port)
CR 30h. (Default 01h)
BIT READ / WRITE DESCRIPTION
7~1 0
Reserved. R/W 0: Logical device is inactive. 1: Activate the logical device.
CR 60h, 61h. (Default 03h, 78h)
BIT READ / WRITE DESCRIPTION
7~0
R/W
These two registers select PRT I/O base address. <100h: FFCh> on 4-byte boundary (EPP not supported) or <100h: FF8h> on 8-byte boundary (all modes supported, EPP is only available when the base address is on 8-byte boundary).
CR 70h. (Default 07h)
BIT READ / WRITE DESCRIPTION
7~4 3~0
Reserved. R/W These bits select IRQ resource for PRT.
CR 74h. (Default 04h)
BIT READ / WRITE DESCRIPTION
7~3 2~0
Reserved. R/W These bits select DRQ resource for PRT. 000: DMA0. 001: DMA1. 010: DMA2. 1xx: No DMA active. 011: DMA3.
CR F0h. (Default 3Fh)
BIT READ / WRITE DESCRIPTION
7 6~3
Reserved. R/W ECP FIFO Threshold. Parallel Port Mode selection (CR28 bit2 PRTMODS2 = 0). 000: Standard and Bi-direction (SPP) mode. 001: EPP - 1.9 and SPP mode. 010: ECP mode. 011: ECP and EPP - 1.9 mode. 100: Printer Mode. 101: EPP - 1.7 and SPP mode. 110: Reserved. 111: ECP and EPP - 1.7 mode.
2~0
R/W
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Publication Release Date: Aug, 22, 2007 Version 1.4
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20.4 Logical Device 2 (UART A)
CR 30h. (Default 01h)
BIT READ / WRITE DESCRIPTION
7~1 0
Reserved. R/W 0: Logical device is inactive. 1: Activate the logical device.
CR 60h, 61h. (Default 03h, F8h)
BIT READ / WRITE DESCRIPTION
7~0
R/W
These two registers select Serial Port 1 I/O base address <100h: FF8h> on 8 bytes boundary.
CR 70h. (Default 04h)
BIT READ / WRITE DESCRIPTION
7~4 3~0
Reserved. R/W These bits select IRQ resource for Serial Port 1.
CR F0h. (Default 00h)
BIT READ / WRITE DESCRIPTION
7~2
Reserved. 00: UART A clock source is 1.8462 MHz (24 MHz / 13). 01: UART A clock source is 2 MHz (24 MHz / 12). 00: UART A clock source is 24 MHz (24 MHz / 1). 00: UART A clock source is 14.769 MHz (24 MHz / 1.625).
1~0
R/W
20.5 Logical Device 3 (UART B)
CR 30h. (Default 01h)
BIT READ / WRITE DESCRIPTION
7~1 0
Reserved. R/W 0: Logical device is inactive. 1: Activate the logical device.
CR 60h, 61h. (Default 02h, F8h)
BIT READ / WRITE DESCRIPTION
7~0
R/W
These two registers select Serial Port 2 I/O base address <100h: FF8h> on eight-byte boundary.
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Publication Release Date: Aug, 22, 2007 Version 1.4
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CR 70h. (Default 03h)
BIT READ / WRITE DESCRIPTION
7~4 3~0
Reserved. R/W These bits select IRQ resource for Serial Port 2.
CR F0h. (Default 00h)
BIT READ / WRITE DESCRIPTION
7~4 3
Reserved. R/W 0: No reception delay when SIR is changed from TX mode to RX mode. 1: Reception delayed for 4 characters' time (40 bit-time) when SIR is changed from TX mode to RX mode. 0: No transmission delay when SIR is changed from RX mode to TX mode. 1: Transmission delayed for 4 characters' time (40 bit-time) when SIR is changed from RX mode to TX mode. 00: UART B clock source is 1.8462 MHz (24 MHz / 13). 01: UART B clock source is 2 MHz (24 MHz / 12). 00: UART B clock source is 24 MHz (24 MHz / 1). 00: UART B clock source is 14.769 MHz (24 MHz / 1.625).
2
R/W
1~0
R/W
CR F1h. (Default 00h)
BIT READ / WRITE DESCRIPTION
7 6 5~3 2
R/W R/W R/W R/W
Reserved. IRLOCSEL => IR I/O pins' location selection. 0: Through SINB / SOUTB. 1: Through IRRX / IRTX. IRMODE => IR function mode selection. See the table below. IR half / full duplex function selection. 0: IR function is Full Duplex. 1: IR function is Half Duplex. 0: SOUTB pin of UART B function or IRTX pin of IR function in normal condition. 1: Inverse SOUTB pin of UART B function or IRTX pin of IR function. 0: SINB pin of UART B function or IRRX pin of IR function in normal condition. 1: Inverse SINB pin of UART B function or IRRX pin of IR function.
1
R/W
0
R/W
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Publication Release Date: Aug, 22, 2007 Version 1.4
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IR MODE
IR FUNCTION
IRTX
IRRX
00X 010* 011* 100 101 110 111*
Disable IrDA IrDA ASK-IR ASK-IR ASK-IR ASK-IR
Tri-state Active pulse 1.6 S Active pulse 3/16 bit time Inverting IRTX/SOUTB pin Inverting IRTX/SOUTB & 500 KHZ clock Inverting IRTX/SOUTB Inverting IRTX/SOUTB & 500 KHZ clock
High Demodulation into SINB/IRRX Demodulation into SINB/IRRX Routed to SINB/IRRX Routed to SINB/IRRX Demodulation into SINB/IRRX Demodulation into SINB/IRRX
Note: The notation is normal mode in the IR function.
20.6 Logical Device 5 (Keyboard Controller)
CR 30h. (Default 01h)
BIT READ / WRITE DESCRIPTION
7~1 0
Reserved. R/W 0: The logical device is inactive. 1: The logical device is active.
CR 60h, 61h. (Default 00h,60h)
BIT READ / WRITE DESCRIPTION
7~0
R/W
These two registers select the first KBC I/O base address <100h: FFFh> on 1-byte boundary.
CR 62h, 63h. (Default 00h,64h)
BIT READ / WRITE DESCRIPTION
7~0
R/W
These two registers select the second KBC I/O base address <100h: FFFh> on 1 byte boundary.
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CR 70h. (Default 01h)
BIT READ / WRITE DESCRIPTION
7~4 3~0
Reserved. R/W These bits select IRQ resource for KINT. (Keyboard interrupt)
CR 72h. (Default 0Ch)
BIT READ / WRITE DESCRIPTION
7~4 3~0
Reserved. R/W These bits select IRQ resource for MINT. (PS/2 Mouse interrupt)
CR F0h. (Default83h)
BIT READ / WRITE DESCRIPTION
7~6
R/W
KBC clock rate selection 00: 6MHz 01: 8MHz 10: 12MHz 11: 16MHz 0: Port 92 disable. 1: Port 92 enable. 0: Gate A20 software control. 1: Gate A20 hardware speed up. 0: KBRST software control. 1: KBRST hardware speed up.
5~3 2 1 0
Reserved. R/W R/W R/W
20.7 Logical Device 6 (Serial Peripheral Interface)
CR 30h. (Default 00h)
BIT READ / WRITE DESCRIPTION
7~1 0
Reserved. R/W 0: Serial Peripheral Interface is inactive. 1: Activate Serial Peripheral Interface.
CR 62h, 63h. (Default 00h)
BIT READ / WRITE DESCRIPTION
7~0
R/W
These two registers select Serial Peripheral Interface I/O base address <100h: FF8h> on 1 byte boundary.
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20.8 Logical Device 7 (GPIO6)
CR 30h. (Default 00h)
BIT READ / WRITE DESCRIPTION
7~4 3 2~0
Reserved. R/W Reserved. 0: GPIO6 is inactive. 1: GPIO6 is active.
CR F4h. (GPIO6 I/O Register; Default FFh)
BIT READ / WRITE DESCRIPTION
7~0
R/W
GPIO6 I/O register 0: The respective GPIO6 PIN is programmed as an output port 1: The respective GPIO6 PIN is programmed as an input port.
CR F5h. (GPIO6 Data Register; Default 00h)
BIT READ / WRITE DESCRIPTION
R/W 7~0 Read Only
GPIO6 Data register For output ports, the respective bits can be read and written by the pins. For input ports, the respective bits can be read only from pins. Write accesses will be ignored.
CR F6h. (GPIO6 Inversion Register; Default 00h)
BIT READ / WRITE DESCRIPTION
7~0
R/W
GPIO6 Inversion register 0: The respective bit and the port value are the same. 1: The respective bit and the port value are inverted. (Applies to both input and output ports)
CR F7h. (Status Register; Default 00h)
BIT READ / WRITE DESCRIPTION
7~0
Read Only Read-Clear
GPIO6 Event Status Bit 7-0 corresponds to GP67-GP60, respectively. 0 : No active edge(rising/falling) has been detected 1 : An active edge(rising/falling) has been detected Read the status bit clears it to 0.
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Publication Release Date: Aug, 22, 2007 Version 1.4
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20.9 Logical Device 8 (WDTO# & PLED)
CR 30h. (Default 00h)
BIT READ / WRITE DESCRIPTION
7~1 0
Reserved. R/W 0: WDTO# and PLED are inactive. 1: Activate WDTO# and PLED.
CR F5h. (WDTO#, PLED and KBC P20 Control Mode Register; Default 00h)
BIT READ / WRITE DESCRIPTION
7~6
R/W
Select Power LED mode. 00: Power LED pin is driven high. 01: Power LED pin is driven low. 10: Power LED pin outputs 1Hz pulse with 50% duty cycle. 11: Power LED pin outputs 0.25Hz pulse with 50% duty cycle. WDTO# count mode is 1000 times faster. 0: Disable. 1: Enable. (If bit-3 is in Second Mode, the count mode is 1/1000 sec.) (If bit-3 is in Minute Mode, the count mode is 1/1000 min.) Select WDTO# count mode. 0: Second Mode. 1: Minute Mode. Enable the rising edge of a KBC reset (P20) to issue a time-out event. 0: Disable. 1: Enable. Disable / Enable the WDTO# output low pulse to the KBRST# pin (PIN60) 0: Disable. 1: Enable.
5
Reserved.
4
R/W
3
R/W
2
R/W
1 0
R/W Reserved.
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Publication Release Date: Aug, 22, 2007 Version 1.4
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CR F6h. (WDTO# Counter Register; Default 00h)
BIT READ / WRITE DESCRIPTION
7~0
R/W
Watch Dog Timer Time-out value. Writing a non-zero value to this register causes the counter to load the value into the Watch Dog Counter and start counting down. If CR F7h, bits 7 and 6 are set, any Mouse Interrupt or Keyboard Interrupt event causes the previously-loaded, non-zero value to be reloaded to the Watch Dog Counter and the count down resumes. Reading this register returns the current value in the Watch Dog Counter, not the Watch Dog Timer Time-out value. 00h: Time-out Disable 01h: Time-out occurs after 1 second/minute 02h: Time-out occurs after 2 second/minutes 03h: Time-out occurs after 3 second/minutes .................................................................. FFh: Time-out occurs after 255 second/minutes
CR F7h. (WDTO# Control & Status Register; Default 00h)
BIT READ / WRITE DESCRIPTION
7
R/W
Mouse interrupt reset enables watch-dog timer reload 0: Watchdog timer is not affected by mouse interrupt. 1: Watchdog timer is reset by mouse interrupt. Keyboard interrupt reset enables watch-dog timer reload 0: Watchdog timer is not affected by keyboard interrupt. 1: Watchdog timer is reset by keyboard interrupt. Trigger WDTO# event. This bit is self-clearing. WDTO# status bit 0: Watchdog timer is running. 1: Watchdog timer issues time-out event. These bits select the IRQ resource for the WDTO#. (02h for SMI# event.)
6 5 4 3~0
R/W Write "1" Only R/W Write "0" Clear R/W
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Publication Release Date: Aug, 22, 2007 Version 1.4
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20.10
BIT
Logical Device 9 (GPIO2, GPIO3, GPIO4, GPIO5)
READ / WRITE DESCRIPTION
CR 30h. (Default 00h) 7~4 3 2 1 0 Reserved. R/W R/W R/W R/W 0: GPIO5 is inactive. 0: GPIO4 is inactive. 0: GPIO3 is inactive. 0: GPIO2 is inactive. 1: GPIO5 is active 1: GPIO4 is active. 1: GPIO3 is active. 1: GPIO2 is active.
CR E0h. (GPIO5 I/O Register; Default FFh)
BIT READ / WRITE DESCRIPTION
7~0
R/W
GPIO5 I/O register 0: The respective GPIO5 PIN is programmed as an output port 1: The respective GPIO5 PIN is programmed as an input port.
CR E1h. (GPIO5 Data Register; Default 00h)
BIT READ / WRITE DESCRIPTION
R/W 7~0 Read Only
GPIO5 Data register For output ports, the respective bits can be read and written by the pins. For input ports, the respective bits can only be read by the pins. Write accesses are ignored.
CR E2h. (GPIO5 Inversion Register; Default 00h)
BIT READ / WRITE DESCRIPTION
7~0
R/W
GPIO5 Inversion register 0: The respective bit and the port value are the same. 1: The respective bit and the port value are inverted. (Applies to both input and output ports)
CR E3h. (GPIO2 Register; Default FFh)
BIT READ / WRITE DESCRIPTION
7~0
R/W
GPIO2 I/O register 0: The respective GPIO2 PIN is programmed as an output port 1: The respective GPIO2 PIN is programmed as an input port
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CR E4h. (GPIO2 Data Register; Default 00h)
BIT READ / WRITE DESCRIPTION
R/W 7~0 Read Only
GPIO2 Data register For output ports, the respective bits can be read and written by the pins. For input ports, the respective bits can only be read by the pins. Write accesses are ignored.
CR E5h. (GPIO2 Inversion Register; Default 00h)
BIT READ / WRITE DESCRIPTION
7~0
R/W
GPIO2 Inversion register 0: The respective bit and the port value are the same. 1: The respective bit and the port value are inverted. (Applies to both input and output ports)
CR E6h. (GPIO2 Status Register; Default 00h)
BIT READ / WRITE DESCRIPTION
7~0
Read Only Read-Clear
GPIO2 Event Status Bit 7-0 corresponds to GP27-GP20, respectively. 0 : No active edge(rising/falling) has been detected 1 : An active edge(rising/falling) has been detected Read the status bit clears it to 0.
CR E7h. (GPIO3 Status Register; Default 00h)
BIT READ / WRITE DESCRIPTION
7~0
Read Only Read-Clear
GPIO3 Event Status Bit 7-0 corresponds to GP37-GP30, respectively. 0 : No active edge(rising/falling) has been detected 1 : An active edge(rising/falling) has been detected Read the status bit clears it to 0.
CR E8h. (GPIO4 Status Register; Default 00h)
BIT READ / WRITE DESCRIPTION
7~0
Read Only Read-Clear
GPIO4 Event Status Bit 7-0 corresponds to GP47-GP40, respectively. 0 : No active edge(rising/falling) has been detected 1 : An active edge(rising/falling) has been detected Reading the status bit clears it to 0.
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CR E9h. (GPIO5 Status Register; Default 00h)
BIT READ / WRITE DESCRIPTION
7
Read Only Read-Clear
GPIO5 Event Status Bit 7-0 corresponds to GP57-GP50, respectively. 0 : No active edge(rising/falling) has been detected 1 : An active edge(rising/falling) has been detected Reading the status bit clears it to 0.
CR F0h. (GPIO3 I/O Register; Default FFh)
BIT READ / WRITE DESCRIPTION
7~0
R/W
GPIO3 I/O register 0: The respective GPIO3 PIN is programmed as an output port 1: The respective GPIO3 PIN is programmed as an input port.
CR F1h. (GPIO3 Data Register; Default 00h)
BIT READ / WRITE DESCRIPTION
R/W 7~0 Read Only
GPIO3 Data register For output ports, the respective bits can be read and written by the pins. For input ports, the respective bits can only be read by the pins. Write accesses are ignored.
CR F2h. (GPIO3 Inversion Register; Default 00h)
BIT READ / WRITE DESCRIPTION
7~0
R/W
GPIO3 Inversion register 0: The respective bit and the port value are the same. 1: The respective bit and the port value are inverted. (Applies to both input and output ports)
CR F3h. (Suspend LED Mode Register; Default 00h) (VBAT power)
BIT READ / WRITE DESCRIPTION
7~6
R/W
Select Suspend LED mode. 00: Suspend LED pin is tri-stated. 01: Suspend LED pin is driven low. 10: Suspend LED pin outputs 1Hz pulse with 50% duty cycle. 11: Suspend LED pin outputs 0.25Hz pulse with 50% duty cycle.
5~0
Reserved.
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CR F4h. (GPIO4 I/O Register; Default FFh)
BIT READ / WRITE DESCRIPTION
7~0
R/W
GPIO4 I/O register 0: The respective GPIO4 PIN is programmed as an output port 1: The respective GPIO4 PIN is programmed as an input port.
CR F5h. (GPIO4 Data Register; Default 00h)
BIT READ / WRITE DESCRIPTION
R/W 7~0 Read Only
GPIO4 Data register For output ports, the respective bits can be read and written by the pins. For input ports, the respective bits can only be read by the pins. Write accesses are ignored.
CR F6h. (GPIO4 Inversion Register; Default 00h)
BIT READ / WRITE DESCRIPTION
7~0
R/W
GPIO4 Inversion register 0: The respective bit and the port value are the same. 1: The respective bit and the port value are inverted. (Applies to both input and output ports)
CR F7h. (GPIO4 Multi-function Select Register; Default 00h)
BIT READ / WRITE DESCRIPTION
7 6 5 4 3 2 1 0
R/W R/W R/W R/W R/W R/W R/W R/W
0: GPIO47 1: GPIO47 0: GPIO46 1: GPIO46 0: GPIO45 1: GPIO45 0: GPIO44 1: GPIO44 0: GPIO43 1: GPIO43 0: GPIO42 1: GPIO42 0: GPIO41 1: GPIO41 0: GPIO40 1: GPIO40
SUSLED WDTO# SUSLED WDTO# SUSLED WDTO# SUSLED WDTO#
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CR FEh. (GPIO3 Input Detected Type Register; Default 00h)
BIT READ / WRITE DESCRIPTION
7 6 5 4 3 2 1 0
R/W R/W R/W R/W Reserved. R/W R/W R/W
Reserved. 0: Enable GP35 input de-bouncer 1: Disable GP35 input de-bouncer 0: Enable GP31 input de-bouncer 1: Disable GP31 input de-bouncer 0: Enable GP30 input de-bouncer 1: Disable GP30 input de-bouncer 0: GP35 trigger type : edge 1: GP35 trigger type : level 0: GP31 trigger type : edge 1: GP31 trigger type : level 0: GP30 trigger type : edge 1: GP30 trigger type : level
20.11
Logical Device A (ACPI)
(CR30, CR70 are VCC powered; CRE0~F7 are VRTC powered) CR 30h. (Default 00h)
BIT READ / WRITE DESCRIPTION
7~1 0
Reserved. R/W 0: Logical device is inactive. 1: Logical device is active.
CR 70h. (Default 00h)
BIT READ / WRITE DESCRIPTION
7~4 3~0
Reserved. R/W These bits select the IRQ resource for PME#.
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Publication Release Date: Aug, 22, 2007 Version 1.4
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CR E0h. (Default 01h)
BIT READ / WRITE
(VBAT power)
DESCRIPTION
7
R/W
DIS_PSIN => Disable the panel switch input to turn on the system power supply. 0: PSIN is wire-AND and connected to PSOUT#. 1: PSIN is blocked and cannot affect PSOUT#. Enable KBC wake-up 0: Disable keyboard wake-up function via PSOUT#. 1: Enable keyboard wake-up function via PSOUT#. Enable Mouse wake-up 0: Disable mouse wake-up function via PSOUT#. 1: Enable mouse wake-up function via PSOUT#. MSRKEY => Three keys (ENMDAT_UP, CRE6[7]; MSRKEY, CRE0[4]; MSXKEY, CRE0[1]) define the combinations of the mouse wake-up events. Please see the following table for the details.
ENMDAT_UP MSRKEY MSXKEY Wake-up event
6
R/W
5
R/W
4
R/W
1 1 0 0 0 0
x x 0 1 0 1
1 0 1 1 0 0
Any button clicked or any movement. One click of left or right button. One click of the left button. One click of the right button. Two clicks of the left button. Two clicks of the right button.
3 2
Reserved. R/W Keyboard / Mouse swap enable 0: Normal mode. 1: Keyboard / Mouse ports are swapped. MSXKEY => Three keys (ENMDAT_UP, CRE6[7]; MSRKEY, CRE0[4]; MSXKEY, CRE0[1]) define the combinations of the mouse wake-up events. Please check out the table in CRE0[4] for the detailed. KBXKEY => 0: Only the pre-determined key combination in sequence can wake up the system. 1: Any character received from the keyboard can wake up the system.
1
R/W
0
R/W
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Publication Release Date: Aug, 22, 2007 Version 1.4
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CR E1h. (KBC Wake-Up Index Register; Default 00h) (VSB power)
BIT READ / WRITE DESCRIPTION
7~0
R/W
Keyboard wake-up index register. This is the index register of CRE2, which is the access window for the keyboard's pre-determined key key-combination characters. The first set of wake-up keys is in of 0x00 - 0x0E, the second set 0x30 - 0x3E, and the third set 0x40 - 0x4E. Incoming key combinations can be read through 0x10 - 0x1E.
CR E2h. (KBC Wake-Up Data Register; Default FFh) (VSB power)
BIT READ / WRITE DESCRIPTION
7~0
R/W
Keyboard wake-up data register. This is the data register for the keyboard's key-combination characters, which is indexed by CRE1.
pre-determined
CR E3h. (Event Status Register; Default 08h)
BIT READ / WRITE DESCRIPTION
7~6 5
Reserved. Read Only Read-Clear
This status flag indicates VSB power off/on. If E4[7] is 1 => 0: When power-loss occurs and the VSB power is on, turn on system power. 1: When power-loss occurs and the VSB power is on, turn off system power. If E4[7] is 0 => This bit is always 0. Thermal shutdown status. 0: No thermal shutdown event issued. 1: Thermal shutdown event issued. PSIN_STS 0: No PSIN event issued. 1: PSIN event issued. MSWAKEUP_STS => The bit is latched by the mouse wake-up event. 0: No mouse wake-up event issued. 1: Mouse wake-up event issued. KBWAKEUP_STS => The bit is latched by the keyboard wake-up event. 0: No keyboard wake-up event issued. 1: Keyboard wake-up event issued.
4
Read Only Read-Clear
3
Read Only Read-Clear Read Only Read-Clear Read Only Read-Clear Read Only Read-Clear
2
1
0
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Publication Release Date: Aug, 22, 2007 Version 1.4
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CR E4h. (Default 00h)
BIT READ / WRITE DESCRIPTION
7
R/W
Disable / Enable to issue a 4s long PSOUT# low pulse when the system returns from power loss state and is supposed to be "off" as described in CRE4[6:5], Logical Device A. (VBAT) 0: Disable. 1: Enable. Power-loss control bits => (VBAT) 00: System always turns off when it returns from power-loss state. 01: System always turns on when it returns from power-loss state. 10: System turns off / on when it returns from power-loss state depending on the state before the power loss. 11: User defines the state before power loss.(i.e. the last state set of CRE6[4]) VSBGATE# Enable bit => 0: Disable. 1: Enable. * This bit is available both for UBE and UBF version Keyboard wake-up options. (LRESET#) 0: Password or sequence hot keys programmed in the registers. 1: Any key. Enable the hunting mode for all wake-up events set in CRE0. This bit is cleared when any wake-up events is captured. (LRESET#) 0: Disable. 1: Enable.
6~5
R/W
4
R/W
3
R/W
2 1~0
R/W Reserved.
CR E5h. (GPIOs Reset Source Register; Default 00))
BIT READ / WRITE DESCRIPTION
7~ 5 4
Reserved. R/W VID_MRST 0: VID reset by LRESET#. 1: VID reset by PWROK. GP23_MRST 0: GP23 reset by LRESET#. 1: GP23 reset by PWROK. GP22_MRST 0: GP22 reset by LRESET#. 1: GP22 reset by PWROK.
3
R/W
2
R/W
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Publication Release Date: Aug, 22, 2007 Version 1.4
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Continued
BIT
READ / WRITE
DESCRIPTION
1
Reserved. ATXPGD signal to control PWROK and PWROK2 generation 0: Enable. 1: Disable. * This bit is available both for UBE and UBF version
0
R/W
CR E6h. (Default 1Ch)
BIT READ / WRITE DESCRIPTION
7 6 5
R/W Reserved. R/W
ENMDAT => (VSB) Three keys (ENMDAT_UP, CRE6[7]; MSRKEY, CRE0[4]; MSXKEY, CRE0[1]) define the combinations of the mouse wake-up events. Please see the table in CRE0, bit 4 for the details. CASEOPEN Clear Control. (VSB) Write 1 to this bit to clear CASEOPEN status. This bit will not clear the status itself. Please write 0 after an event is cleared. The function is the same as Index 46h bit 7 of H/W Monitor part. Power-loss Last State Flag. (VBAT) 0: ON 1: OFF. PWROK_DEL (first stage) (VSB) Set the delay time when rising from PWROK_LP to PWROK_ST. 0: 300 ~ 500 mS. 1: 200 ~ 300 mS. PWROK_DEL (VSB) Set the delay time when rising from PWROK_ST to PWROK. 00: No delay time. 01: Delay 32 mS 10: 96 mS 11: Delay 250 mS
PWROK_TRIG => Write 1 to re-trigger the PWROK signal from low to high.
4
R/W
3
R/W
2~1
R/W
0
R / W-Clear
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Publication Release Date: Aug, 22, 2007 Version 1.4
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CR E7h. (Default 00h)
BIT READ / WRITE DESCRIPTION
7
R/W
ENKD3 => (VSB) Enable the third set of keyboard wake-up key combination. Its values are accessed through keyboard wake-up index register (CRE1) and keyboard wake-up data register (CRE2) at the index from 40h to 4eh. 0: Disable the third set of the key combinations. 1: Enable the third set of the key combinations. ENKD2 => (VSB) Enable the second set of keyboard wake-up key combination. Its values are accessed through keyboard wake-up index register (CRE1) and keyboard wake-up data register (CRE2) at the index from 30h to 3eh. 0: Disable the second set of the key combinations. 1: Enable the second set of the key combinations. ENWIN98KEY => (VSB) Enable Win98 keyboard dedicated key to wake-up system via PSOUT# when keyboard wake-up function is enabled. 0: Disable Win98 keyboard wake-up. 1: Enable Win98 keyboard wake-up. EN_ONPSOUT (VBAT) Disable/Enable to issue a 0.5s long PSOUT# low pulse when system returns from power loss state and is supposed to be on as described in CRE4[6:5], logic device A. (for SiS & VIA chipsets) 0: Disable. 1: Enable. Select WDTO# reset source (VSB) 0: Watchdog timer is reset by LRESET#. 1: Watchdog timer is reset by PWROK. Hardware Monitor RESET source select (VBAT) 0: PWROK. 1: LRESET#.
6
R/W
5
R/W
4
R/W
3 2~1 0
R/W Reserved. R/W
CR E8h. (Reserved) CR E9h. (Reserved)
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CR F2h. (Default 7Ch) (VSB Power)
BIT READ / WRITE DESCRIPTION
7 6
Reserved. R/W Enable RSTOUT4# function. 0: Disable RSTOUT4#. 1: Enable RSTOUT4#. Enable RSTOUT3# function. 0: Disable RSTOUT3#. 1: Enable RSTOUT3#. Enable RSTOUT2# function. 0: Disable RSTOUT2#. 1: Enable RSTOUT2#. Enable RSTOUT1# function. 0: Disable RSTOUT1#. 1: Enable RSTOUT1#. Enable RSTOUT0# function. 0: Disable RSTOUT0#. 1: Enable RSTOUT0#. EN_PME => 0: Disable PME. 1: Enable PME.
5
R/W
4
R/W
3
R/W
2 1 0
R/W Reserved. R/W
CR F3h. (Default 00h)
BIT READ / WRITE DESCRIPTION
7~6 5 4 3 2 1 0
Reserved. R / W-Clear R / W-Clear R / W-Clear R / W-Clear R / W-Clear R / W-Clear PME status of the Mouse IRQ event. Write 1 to clear this status. PME status of the KBC IRQ event. Write 1 to clear this status. PME status of the PRT IRQ event. Write 1 to clear this status. PME status of the FDC IRQ event. Write 1 to clear this status. PME status of the URA IRQ event. Write 1 to clear this status. PME status of the URB IRQ event. Write 1 to clear this status.
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Publication Release Date: Aug, 22, 2007 Version 1.4
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CR F4h. (Default 00h)
BIT READ / WRITE DESCRIPTION
7~4 3 2 1 0
Reserved. R / W-Clear R / W-Clear Reserved. R / W-Clear PME status of the RIB event. Write 1 to clear this status. PME status of the HM IRQ event. Write 1 to clear this status. PME status of the WDTO# event. Write 1 to clear this status.
CR F6h. (Default 00h) (VSB Power)
BIT READ / WRITE DESCRIPTION
7~6 5 4 3 2 1 0
Reserved. R/W R/W R/W R/W R/W R/W 0: Disable PME interrupt of the Mouse IRQ event. 1: Enable PME interrupt of the Mouse IRQ event. 0: Disable PME interrupt of the KBC IRQ event. 1: Enable PME interrupt of the KBC IRQ event. 0: Disable PME interrupt of the PRT IRQ event. 1: Enable PME interrupt of the PRT IRQ event. 0: Disable PME interrupt of the FDC IRQ event. 1: Enable PME interrupt of the FDC IRQ event. 0: Disable PME interrupt of the URA IRQ event. 1: Enable PME interrupt of the URA IRQ event. 0: Disable PME interrupt of the URB IRQ event. 1: Enable PME interrupt of the URB IRQ event.
CR F7h. (Default 00h) (VSB Power)
BIT READ / WRITE DESCRIPTION
7~4 3 2 1 0
Reserved. R/W R/W Reserved. R/W 0: Disable PME interrupt of the RIB event. 1: Enable PME interrupt of the RIB event. 0: Disable PME interrupt of the HM IRQ event. 1: Enable PME interrupt of the HM IRQ event. 0: Disable PME interrupt of the WDTO# event. 1: Enable PME interrupt of the WDTO# event.
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CR FEh. (GPIO3 Event Route Selection Register; Default 00h)
BIT READ / WRITE DESCRIPTION
7 6 5 4 3 2 1 0
R/W R/W R/W R/W Reserved. R/W R/W R/W
Reserved. 0: Disable GP35 event route to PSOUT#. 1: Enable GP35 event route to PSOUT#. 0: Disable GP31 event route to PSOUT#. 1: Enable GP31 event route to PSOUT#. 0: Disable GP30 event route to PSOUT#. 1: Enable GP30 event route to PSOUT#. 0: Disable GP35 event route to PME#. 1: Enable GP35 event route to PME#. 0: Disable GP31 event route to PME#. 1: Enable GP31 event route to PME#. 0: Disable GP30 event route to PME#. 1: Enable GP30 event route to PME#.
20.12
BIT
Logical Device B (Hardware Monitor)
READ / WRITE DESCRIPTION
CR 30h. (Default 00h) 7~1 0 Reserved. R/W 0: Logical device is inactive. 1: Logical device is active.
CR 60h, 61h. (Default 00h, 00h)
BIT READ / WRITE DESCRIPTION
7~0
R/W
These two registers select the HM base address <100h : FFEh> along a two-byte boundary.
CR 70h. (Default 00h)
BIT READ / WRITE DESCRIPTION
7~4 3~0
Reserved. R/W These bits select the IRQ resource for HM.
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CR F0h. (VID Control Register; Default 81h)
BIT READ / WRITE DESCRIPTION
7
R/W
VID I/O Control 0: VID output mode. 1: VID input mode. VIDAMD input level select 0: VID is GTL level. 1: VID is AMD VRM level.
6 5-0
R/W Reserved.
CR F1h. (VID Data Register; Default 00h)
BIT READ / WRITE DESCRIPTION
7~0
R/W
VID[7:0] Data Register. (For Input/Output both use)
CR F2h. (FAN Strapping Status Register; Default 00h) (VCC Power)
BIT READ / WRITE DESCRIPTION
7~2
Reserved. FAN_SET2 strapping status. This bit is strapped by pin 83(SOUTB). 0: Initial speed is 100%. 1: Initial speed is 50%. FAN_SET strapping status. This bit is strapped by pin 117(PLED). 0: Initial speed is 100%. 1: Initial speed is 50%.
1
Read Only
0
Read Only
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20.13
BIT
Logical Device C (PECI, SST)
READ / WRITE DESCRIPTION
CR E0h. (Agent Configuration Register; Default 00h) Agt4EN (Agent 4 Enable Bit) 0: Agent 4 is disabled. 1: Agent 4 is enabled. Agt3EN (Agent 3 Enable Bit) 0: Agent 3 is disabled. 1: Agent 3 is enabled. Agt2EN (Agent 2 Enable Bit) 0: Agent 2 is disabled. 1: Agent 2 is enabled. Agt1EN (Agent 1 Enable Bit) 0: Agent 1 is disabled. 1: Agent 1 is enabled. RTD4 (Agent 4 Return Domain 1 Enable Bit. Functions only when Agt4D1 is set to 1) 0: Agent 4 always returns the relative temperature from domain 0. 1: Agent 4 always returns the relative temperature from domain 1. RTD3 (Agent 3 Return Domain 1 Enable Bit. Functions only when Agt3D1 is set to 1) 0: Agent 3 always returns the relative temperature from domain 0. 1: Agent 3 always returns the relative temperature from domain 1. RTD2 (Agent 2 Return Domain 1 Enable Bit. Functions only when Agt2D1 is set to 1) 0: Agent 2 always returns the relative temperature from domain 0. 1: Agent 2 always returns the relative temperature from domain 1. RTD1 (Agent 1 Return Domain 1 Enable Bit. Functions only when Agt1D1 is set to 1) 0: Agent 1 always returns the relative temperature from domain 0. 1: Agent 1 always returns the relative temperature from domain 1.
7
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
R/W
Note. Agent 1 ~ Agent 4 represent the addresses of PECI devices is from 0x30h to 0x33h respectively.
CR E1h. (Agent 1 TBase Register; Default 48h)
BIT READ / WRITE DESCRIPTION
7 6~0
Reserved R/W Agent 1 TBase must always be a positive value; a negative value will cause abnormal temperature responses. (Note 1)
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CR E2h. (Agent 2 TBase Register; Default 48h)
BIT READ / WRITE DESCRIPTION
7 6~0
Reserved. R/W Agent 2 TBase must always be a positive value; a negative value will cause abnormal temperature responses. (Note 1)
CR E3h. (Agent 3 TBase Register; Default 48h)
BIT READ / WRITE DESCRIPTION
7 6~0
Reserved. R/W Agent 3 TBase must always be a positive value; a negative value will cause abnormal temperature responses. (Note 1)
CR E4h. (Agent 4 TBase Register; Default 48h)
BIT READ / WRITE DESCRIPTION
7 6~0
Reserved. R/W Agent 4 TBase must always be a positive value; a negative value will cause abnormal temperature responses. (Note 1)
Note 1: TBase is a temperature reference based on the experiment of processor actual temperature. For more detail, please refer to Chapter 7.5.
CR E5h. (PECI Register; Default 00h)
BIT READ / WRITE DESCRIPTION
7
R/W
Agt4D1 (Agent 4 Domain 1 Enable Bit) 0: Agent 4 does not have domain 1. 1: Agent 4 has domain 1. Agt3D1 (Agent 3 Domain 1 Enable Bit) 0: Agent 3 does not have domain 1. 1: Agent 3 has domain 1. Agt2D1 (Agent 2 Domain 1 Enable Bit) 0: Agent 2 does not have domain 1. 1: Agent 2has domain 1. Agt1D1 (Agent 1 Domain 1 Enable Bit) 0: Agent 1 does not have domain 1. 1: Agent 1 has domain 1.
6
R/W
5
R/W
4
R/W
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Continued
BIT
READ / WRITE
DESCRIPTION
3~2
Reserved Return High Temperature 0: The temperature of each agent is returned from domain 0 or domain 1, which is controlled by CRE0 bit 0~3. 1: Return the highest temperature in domain 0 and domain 1 of individual Agent. PECISB_EN: 0: PECI host is controlled by IO 1: PECI host is the other (i.e. South Bridge).
1
R/W
0
R/W
CR E8h. (PECI Warning Flag Register; Default 00h)
BIT READ / WRITE DESCRIPTION
7
R/W
Agent 4 Absent / Alert Bit 0: Agent 4 is detected and has valid FCS 1: Agent 4 cannot be detected or has invalid FCS in the previous 3 transactions Agent 3 Absent / Alert Bit 0: Agent 3 is detected and has valid FCS 1: Agent 3 cannot be detected or has invalid FCS in the previous 3 transactions Agent 2 Absent / Alert Bit 0: Agent 2 is detected and has valid FCS 1: Agent 2 cannot be detected or has invalid FCS in the previous 3 transactions Agent 1 Absent / Alert Bit 0: Agent 1 is detected and has valid FCS 1: Agent 1 cannot be detected or has invalid FCS in the previous 3 transactions PECI speed selected 00: The PECI speed is 1.5 MHz 01: The PECI speed is 750 KHz 10: The PECI speed is 375 KHz 11: The PECI speed is 187.5 KHz
6
R/W
5
R/W
4
R/W
3~2
Reserved.
1~0
R/W
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CR F1h. (SST Address Register; Default 48h)
BIT READ / WRITE DESCRIPTION
7~0
R/W
SST address
CR FEh. (PECI Agent Relative Temperature Register; Default 00h)
BIT READ / WRITE DESCRIPTION
7~0
Read Only
This register shows the retrieved High Byte raw data from PECI interface.
CR FFh. (PECI Agent Relative Temperature Register; Default 00h)
BIT READ / WRITE DESCRIPTION
7~0
Read Only
This register shows the retrieved Low Byte raw data from PECI interface
Note: PECI relative temperature data is formatted in a 16-bit two's complement value representing a number of 1/64C.
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21. SPECIFICATIONS 21.1 Absolute Maximum Ratings
SYMBOL PARAMETER RATING UNIT
3VCC
Power Supply Voltage (3.3V) Input Voltage Input Voltage (5V tolerance) RTC Battery Voltage VBAT Operating Temperature Storage Temperature
-0.5 to 6.5 -0.5 to 3VCC+0.5 -0.5 to 6 2.2 to 4.0 0 to +70 -55 to +150
V V V V C C
VI VBAT TA TSTG
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
21.2 DC CHARACTERISTICS
(Ta = 0C to 70C, VDD = 3.3V 5%, VSS = 0V)
PARAMETER SYM MIN
TYP
MAX.
UNIT
CONDITIONS
RTC Battery Quiescent Current ACPI Stand-by Power Supply Quiescent Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage
IBAT ISB
2.4 2.0
A mA
VBAT = 2.5 V VSB = 3.3 V, All ACPI pins are not connected.
I/O8t - TTL-level, bi-directional pin with 8mA source-sink capability VIL VIH VOL VOH ILIH ILIL VIL VIH VOL VOH ILIH ILIL 2.4 +10 -10 2.0 0.4 2.4 +10 -10 0.8 2.0 0.4 0.8 V V V V A A V V V V A A IOL = 12 mA IOH = -12 mA VIN = 3.3V VIN = 0V IOL = 8 mA IOH = - 8 mA VIN = 3.3V VIN = 0V
I/O12t - TTL-level, bi-directional pin with 12mA source-sink capability
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DC CHARACTERISTICS, continued
PARAMETER
SYM
MIN
TYP
MAX.
UNIT
CONDITIONS
I/O24t - TTL-level, bi-directional pin with 24mA source-sink capability Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL VIL VIH VOL VOH ILIH ILIL VtVt+ VTH VOL VOH ILIH ILIL VtVt+ VTH VOL VOH ILIH ILIL 2.4 +10 -10 0.5 1.6 0.5 0.8 2.0 1.2 0.4 2.4 +10 -10 1.1 2.4 0.5 1.6 0.5 0.8 2.0 1.2 0.4 2.4 +10 -10 1.1 2.4 2.0 0.4 2.4 +10 -10 0.8 2.0 0.4 0.8 V V V V A A V V V V A A V V V V V A A V V V V V A A VCC= 3.3V IOL = 24 mA IOH = -24 mA VIN = 3.3V VIN = 0V VCC=3.3V IOL = 12 mA IOH = -12 mA VIN = 3.3V VIN = 0V IOL = 12 mA IOH = -12 mA VIN = 3.3V VIN = 0V IOL = 24 mA IOH = -24 mA VIN = 3.3V VIN = 0V
I/O12tp3 - 3.3V TTL-level, bi-directional pin with 12mA source-sink capability
I/O12ts - TTL-level, Schmitt-trigger, bi-directional pin with 12mA source-sink capability
I/O24ts - TTL-level, Schmitt-trigger, bi-directional pin with 24mA source-sink capability
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DC CHARACTERISTICS, continued
PARAMETER
SYM
MIN
TYP
MAX.
UNIT
CONDITIONS
I/O24tsp3 - 3.3V TTL-level, Schmitt-trigger, bi-directional pin with 24mA source-sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage Input Low Voltage Input High Voltage Output Low Voltage Input High Leakage Input Low Leakage Input Low Voltage Input High Voltage Output Low Voltage Input High Leakage Input Low Leakage Input Low Voltage Input High Voltage Output Low Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL VOH ILIH ILIL VIL VIH VOL ILIH ILIL VIL VIH VOL ILIH ILIL VIL VIH VOL ILIH ILIL 2.0 0.4 +10 -10 2.0 0.4 +10 -10 0.8 2.0 0.4 +10 -10 0.8 2.4 +10 -10 0.8 0.5 1.6 0.5 0.8 2.0 1.2 0.4 1.1 2.4 V V V V V A A V V V A A V V V A A V V V A A IOL = 24 mA VIN = 3.3V VIN = 0V IOL = 16 mA VIN = 3.3V VIN = 0V IOL = 12 mA VIN = 3.3V VIN = 0V VCC=3.3V IOL = 24 mA IOH = -24 mA VIN = 3.3V VIN = 0V
I/OD12t - TTL-level, bi-directional pin and open-drain output with 12mA sink capability
I/OD16t - TTL-level, bi-directional pin and open-drain output with 16mA sink capability
I/OD24t - TTL-level, bi-directional pin and open-drain output with 24mA sink capability
I/O12tp3 - 3.3V TTL-level, bi-directional pin and open-drain output with 12mA source-sink capability Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 2.4 +10 -10 2.0 0.4 0.8 V V V V A A IOL = 12 mA IOH = -12 mA VIN = 3.3V VIN = 0V
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DC CHARACTERISTICS, continued
PARAMETER
SYM
MIN
TYP
MAX.
UNIT
CONDITIONS
I/OD16ts - TTL-level, Schmitt-trigger, bi-directional pin and open-drain output with 16mA sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL ILIH ILIL 0.5 1.6 0.5 0.8 2.0 1.2 0.4 +10 -10 1.1 2.4 V V V V A A VCC=3.3V IOL = 16 mA VIN = 3.3V VIN = 0V
I/OD24ts - TTL level, Schmitt-trigger, bi-directional pin and open-drain output with 24mA sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL ILIH ILIL 0.5 1.6 0.5 0.8 2.0 1.2 0.4 +10 -10 1.1 2.4 V V V V A A VCC=3.3V IOL = 24 mA VIN = 3.3V VIN = 0V
I/OD12cs - CMOS-level, Schmitt-trigger, bi-directional pin and open-drain output with 12mA sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL ILIH ILIL 0.5 1.6 0.5 0.8 2.0 1.2 0.4 +10 -10 1.1 2.4 V V V V A A VCC = 3.3 V VCC = 3.3 V VCC = 3.3 V IOL = 12 mA VIN = 3.3 V VIN = 0 V
I/OD16cs - CMOS-level, Schmitt-trigger, bi-directional pin and open-drain output with 16mA sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL ILIH ILIL 0.5 1.6 0.5 0.8 2.0 1.2 0.4 +10 -10 1.1 2.4 V V V V A A VCC = 3.3 V VCC = 3.3 V VCC = 3.3 V IOL = 16 mA VIN = 3.3 V VIN = 0 V
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DC CHARACTERISTICS, continued
PARAMETER
SYM
MIN
TYP
MAX.
UNIT
CONDITIONS
I/OD12csd - CMOS-level, Schmitt-trigger, bi-directional pin with internal pulled-down resistor and open-drain output with 12mA sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL ILIH ILIL 0.5 1.6 0.5 0.8 2.0 1.2 0.4 +10 -10 1.1 2.4 V V V V A A VCC = 3.3 V VCC = 3.3 V VCC = 3.3 V IOL = 12 mA VIN = 3.3 V VIN = 0 V
I/OD12csu - CMOS-level, Schmitt-trigger, bi-directional pin with internal pulled-up resistor and open-drain output with 12mA sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Input High Leakage Input Low Leakage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage VtVt+ VTH VOL ILIH ILIL VOL VOH VOL VOH VOL VOH VOL VOH VOL VOH 2.4 2.4 0.4 2.4 0.4 2.4 0.4 2.4 0.4 0.5 1.6 0.5 0.8 2.0 1.2 0.4 +10 -10 0.4 1.1 2.4 V V V V A A V V V V V V V V V V VCC = 3.3 V VCC = 3.3 V VCC = 3.3 V IOL = 12 mA VIN = 3.3 V VIN = 0 V IOL = 4 mA IOH = -4 mA IOL = 8 mA IOH = -8 mA IOL = 12 mA IOH = -12 mA IOL = 16 mA IOH = -16 mA IOL = 24 mA IOH = -24 mA
O4 - Output pin with 4mA source-sink capability
O8 - Output pin with 8mA source-sink capability
O12 - Output pin with 12mA source-sink capability
O16 - Output pin with 16mA source-sink capability
O24 - Output pin with 24mA source-sink capability
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DC CHARACTERISTICS, continued
PARAMETER
SYM
MIN
TYP
MAX.
UNIT
CONDITIONS
O12p3 - 3.3V output pin with 12mA source-sink capability Output Low Voltage Output High Voltage VOL VOH 2.4 0.4 V V IOL = 12 mA IOH = -12 mA
O24p3 - 3.3V output pin with 24mA source-sink capability Output Low Voltage Output High Voltage VOL VOH 2.4 0.4 V V IOL = 24 mA IOH = -24 mA
OD12 - Open-drain output pin with 12mA sink capability Output Low Voltage VOL 0.4 V IOL = 12 mA
OD24 - Open-drain output pin with 24mA sink capability Output Low Voltage VOL 0.4 V IOL = 24 mA
OD12p3 - 3.3V open-drain output pin with 12mA sink capability Output Low Voltage INt - TTL-level input pin Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage INtp3 - 3.3V TTL-level input pin Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage VIL VIH ILIH ILIL 2.0 +10 -10 0.8 V V A A VIN = 3.3V VIN = 0 V VIL VIH ILIH ILIL 2.0 +10 -10 0.8 V V A A VIN = 3.3 V VIN = 0 V VOL 0.4 V IOL = 12 mA
INtd - TTL-level input pin with internal pulled-down resistor Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage VIL VIH ILIH ILIL 2.0 +10 -10 0.8 V V A A VIN = 3.3 V VIN = 0 V
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DC CHARACTERISTICS, continued
PARAMETER
SYM
MIN
TYP
MAX.
UNIT
CONDITIONS
INtu - TTL-level input pin with internal pulled-up resistor Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage INc - CMOS-level input pin Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage VIL VIH ILIH ILIL 0.7 VCC +10 -10 0.3 VCC 0.7 VCC +10 -10 0.3 VCC 0.3 VCC V V A A VIN = VCC = 3.3V VIN = 0 V VIL VIH ILIH ILIL VtVt+ VTH ILIH ILIL VtVt+ VTH ILIH ILIL 0.5 1.6 0.5 0.8 2.0 1.2 +10 -10 0.5 1.6 0.5 0.8 2.0 1.2 +10 -10 1.1 2.4 2.0 +10 -10 1.1 2.4 0.8 V V A A V V V A A V V V A A VIN = 3.3 V VIN = 0 V VCC = 3.3 V VCC = 3.3 V VCC = 3.3 V VIN = 3.3 V VIN = 0 V VCC = 3.3 V VCC = 3.3 V VCC = 3.3 V VIN = 3.3 V VIN = 0 V
INts - TTL-level, Schmitt-trigger input pin
INtsp3 - 3.3 V TTL-level, Schmitt-trigger input pin
INcd - CMOS-level input pin with internal pulled-down resistor Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage Input Low Voltage VIL VIH ILIH ILIL VIL V V A A V VIN = VCC = 3.3V VIN = 0 V
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DC CHARACTERISTICS, continued
PARAMETER
SYM
MIN
TYP
MAX.
UNIT
CONDITIONS
INcu - CMOS-level input pin with internal pulled-up resistor Input High Voltage Input High Leakage Input Low Leakage Input Low Threshold Voltage Hystersis Input High Leakage Input Low Leakage Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage AOUT - Analog output N.A. INBV1S - VID input pin for INTEL(R) VRM10.0, and VRM11 design
B
VIH ILIH ILIL VtVTH ILIH ILIL VtVt+ VTH ILIH ILIL
0.7 VCC +10 -10 1.3 1.5 1.5 2 +10 -10 0.5 1.6 0.5 0.8 2.0 1.2 +10 -10 1.1 2.4 1.7
V A A V V A A V V V A A VIN = VCC = 3.3V VIN = 0 V VCC = 3.3V VCC = 3.3V VIN = 3.3V VIN = 0 V VCC = 3.3V VCC = 3.3V VCC = 3.3V VIN = 3.3V VIN = 0 V
INcs - CMOS-level, Schmitt-trigger input pin
INcsu - CMOS-level, Schmitt-trigger input pin with internal pulled-up resistor
Input Low Voltage Input High Voltage
B
VIL VIH 0.6
0.4
V V
INBV2S - VID input pin for AMDTMVRM design Input Low Voltage Input High Voltage VIL VIH 1.4 0.8 V V
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DC CHARACTERISTICS, continued
PARAMETER
B
SYM
MIN
TYP
MAX.
UNIT
CONDITIONS
I/OBV3 - Bi-direction pin with source capability of 6 mA and sink capability of 1 mA for INTEL(R) PECI Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Hysterisis
B
VIL VIH VOL VOH VHys
0.275Vtt 0.55Vtt
0.5Vtt 0.725Vtt 0.25Vtt
V V V V V
0.75Vtt 0.1Vtt
I/OBV4 - Bi-direction pin with source capability of 6 mA and sink capability of 1 mA for INTEL(R) SST Input Low Threshold Voltage Input High Threshold Voltage Input High Leakage Input Low Leakage Hysteresis VtVt+ ILIH ILIL VTH 0.15 0.4 0.75 0.65 1.1 +10 -10 V V A A V Vcc = 1.5 V Vcc = 1.5 V VIN = Vcc VIN = 0V Vcc = 1.5 V
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21.3 AC CHARACTERISTICS
21.3.1 AC Power Failure Resume Timing 1. Logical Device A, CR[E4h] bit7 = "0" and CR[E4h] bits[6:5] are selected to "OFF" state ("OFF" means always being turned off or the previous state is off)
3VCC
PSOUT#
PSON# SUSB#
RSMRST#
3VSB
ACLOSS
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2. Logical Device A, CR[E4h] bit7 = "0" and CR[E4h] bits[6:5] are selected to "ON" state ("ON" means always being turned on or the previous state is on)
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3. Logical Device A, CR[E4h] bit7 = "1" and CR[E4h] bits[6:5] are selected to "OFF" state ("OFF" means always being turned off or the previous state is off)
3VCC
PSOUT# T 4S
PSON# SUSB# RSMRST#
3VSB
ACLOSS
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4. Logical Device A, CR[E4h] bit7 = "1" and CR[E4h] bits[6:5] are selected to "ON" state ("ON" means always being turned on or the previous state is on)
3VCC
PSOUT#
PSON# SUSB#
RSMRST#
3VSB
ACLOSS
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** What's the definition of former state at AC power failure? 1) The previous state is "ON" 3VCC falls to 2.6V and SUSB# keeps at VIH 2.0V
3VCC
SUSB#
2) The previous state is "OFF" 3VCC falls to 2.6V and SUSB# keeps at VIL 0.8V
3VCC
SUSB#
To ensure that VCC does not fall faster than VSB in various ATX Power Supplies, the W83627DHG adds the option of "user define mode" for the pre-defined state before AC power failure. BIOS can set the pre-defined state to be "On" or "Off". According to this setting, the system chooses the state after the AC power recovery. Logical Device A, CR E4h Power-loss control bits => (VBAT) 00: System always turns off when it returns from power-loss state. 01: System always turns on when it returns from power-loss state. 6~5 R/W 10: System turns off / on when it returns from power-loss state depending on the state before the power loss. 11: User defines the state before the power loss.(The previous state is set at CRE6[4])
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
Logical Device A, CR E6h 4 R/W Power loss Last State Flag. (VBAT) 0: ON 1: OFF
21.3.2 VSBGATE# Timing - for UBE and UBF Version Only
VSBGATE# drives low only when SUSB# is active and Logical Device A, CR[E4h] bit 4 is set to "1
VSBGATE# is reset to high after PSON# is active
VSBGATE#
t2
t1
3VCC PSON#
t4 t3
SUSB#
SUSC#
S0
SYMBOL t1 t2 t3 t4
S3
PARAMETER
S0
MIN 0 90 0 28 MAX 80 142 80 39 UNIT nS mS nS mS
SUSB# active to VSBGATE# active PSON# active to VSBGATE# inactive SUSB# inactive to PSON# active SUSB# active to PSON# inactive
Note. The values above the worst-case results of R&D simulation
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
21.3.3 Clock Input Timing
PARAMETER MIN 48MHZ / 24MHZ MAX UNIT
Cycle to cycle jitter Duty cycle 45
300/500 55
ps %
t1 t2
t3
PARAMETER
DESCRIPTION MIN
48MHZ / 24MHZ TYP MAX
UNIT
t1 t2 t3
Clock cycle time Clock high time/low time Clock rising time/falling time (0.4V~2.4V) 9 / 19
20.8 / 41.7 10 / 21 3
ns ns ns
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
21.3.4 PECI and SST Timing
SST / PECI
Logic - 1
Minimum tH1 Maximum tH1
Previous bit
tBIT
Next-bit
SST / PECI
Logic - 0
Minimum tH0
Maximum tH0
Previous bit
tBIT
Next-bit
SYMBOL
MIN
TYP
MAX
UNITS
tBIT
Client Originator tH1 tH0
0.495 0.495 0.6 0.2 3/4 1/4
500 250 0.8
s x tBIT
0.4
x t BIT
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
21.3.5 SPI Timing
t1 t2
SCE
t3
SCK SO
t4
SI
t5
DESCRIPTION SYMBOL MIN TYP MAX
Enable to first clock falling Disable after last clock rising Output hold time Input setup time Input hold time
t1 t2 t3 t4 t5
25ns 40ns 5ns 6ns
-
35ns 50ns 5ns -
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
21.3.6 SMBus Timing
TLOW TR SMBCLK TF
THIGH THD:STA THD:DAT SMBDAT
TSU:DAT TSU:STA
TSU:STO
TBUF
P
S
S
P
SYMBOL
PARAMETER
MIN.
MAX.:
UNITS
TBUF THD:STA TSU:STA TSU:STO THD:DAT TSU:DAT TLOW THIGH TF TR
Bus Free Time between Stop and Start Condition Hold time after (Repeated) Start Condition. After this period, the first clock is generated Repeated Start Condition setup time Stop Condition setup time Data hold time Data setup time Clock low period Clock high period Clock/Data Falling Time Clock/Data Rising Time
4.7 4.0 4.7 4.0 300 250 4.7 4.0 -
50 300 1000
uS uS uS uS nS nS uS uS nS nS
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
21.3.7 Floppy Disk Drive Timing FDC: Data rate = 1MB, 500KB, 300KB, 250KB/sec.
PARAMETER SYM. MIN. TYP. (NOTE 1) MAX. UNIT
DIR# setup time to STEP# DIR# hold time from STEP# STEP# pulse width STEP# cycle width INDEX# pulse width RDATA# pulse width WD# pulse width
Notes: 1. 2.
TDST TSTD TSTP TSC TIDX TRD TWD
1.0/1.6 /2.0/4.0 24/40 /48/96 6.8/11.5 /13.8/27.8 NOTE 2 125/250 /417/500 40 100/185 /225/475 125/210 /250/500 150/235 /275/525 7/11.7 /14/28 NOTE 2 7.2/11.9 /14.2/28.2 NOTE 2
S S S mS nS nS nS
Typical values for T = 25C and normal supply voltage. Programmable from 0.5 mS through 32 mS as described in step rate table. (Please refer to the description of the SPECIFY command set.)
Step Rate Table
DATA RATE SRT 1MB/S 500KB/S 300KB/S 250KB/S
0 1 ... E F
8 7.5 ... 1.0 0.5
16 15 ... 2 1 Floppy Disk Driving Timing
26.7 25 ... 3.33 1.67
32 30 ... 4 2
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
TSTD DIR# TSTP TDST STEP# TSC
TIDX INDEX# TRD RDATA# TWD WD#
21.3.8 UART/Parallel Port
PARAMETER SYMBOL TEST CONDITIONS MIN. MAX. UNIT
Delay from Stop to Set Interrupt Delay from IOR Reset Interrupt Delay from Initial IRQ Reset to Transmit Start Delay from to Reset interrupt Delay from Initial IOW to interrupt Delay from Stop to Set Interrupt Delay from
IOR to Reset Interrupt
TSINT TRINT TIRS THR TSI TSTI TIR TMWO TSIM TRIM
N
9/16 9 1/16 1000 8/16 175 9/16 16/16 8/16 8 6 18 9 100 pF Loading 250 200 250 250 2 -1
16
Baud Rate nS Baud Rate nS Baud Rate Baud Rate nS nS nS nS
Delay from IOR to Output Set Interrupt Delay from Modem Input Reset Interrupt Delay from IOR Baud Divisor
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
UART Receiver Timing
Receiver Timing
SIN (RECEIVER INPUT DATA)
START DATA BITS (5-8) PARITY
TSINT
STOP
IRQ (INTERNAL SIGNAL)
TSTI
IRQ# (INTERNAL SIGNAL. READ RECEIVER BUFFER REGISTER)
UART Transmitter Timing
SOUT (SERIAL OUT)
START
DATA BITS (5-8)
TIRS
IRQ (INTERNAL SIGNAL)
PARITY
STOP (1-2) TSTI
START
THR TSI THR
IOW# (INTERNAL SIGNAL, WRITE THR)
TIR
IOR# (INTERNAL SIGNAL, READ TIR)
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
21.3.8.1. Modem Control Timing
MODEM Control Timing
IOW# (INTERNAL SIGNAL, WRITE MCR)
START
TMWO RTS#, DTR#
TMWO
CTS#, DSR#, DCD# TSIM IRQ (INTERNAL SIGNAL) IOR# (INTERNAL SIGNAL READ MSR) RI# TSIM
TRIM
TRIM
TSIM
21.3.9
Parallel Port Mode Parameters
PARAMETER SYM. MIN. TYP. MAX. UNIT
PD0-7, INDEX , STROBE , AUTOFD Delay from IOW IRQ Delay from ACK , nFAULT IRQ Delay from IOW IRQ Active Low in ECP and EPP Modes
ERROR Active to IRQ Active
t1 t2 t3 t4 t5 t1 t2 t3 t4 t5 200 200
100 60 105 300 105 100 60 105 300 105
nS nS nS nS nS nS nS nS nS nS
PD0-7, INDEX , STROBE , AUTOFD Delay from IOW IRQ Delay from ACK , nFAULT IRQ Delay from IOW IRQ Active Low in ECP and EPP Modes
ERROR Active to IRQ Active
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
21.3.10 Parallel Port
21.3.10.1. Parallel Port Timing
IOW
t1
INIT, STROBE AUTOFD, SLCTIN PD<0:7>
ACK t2
IRQ (SPP)
IRQ (EPP or ECP) nFAULT (ECP) ERROR (ECP)
t3
t4
t5
IRQ
t2
t4
21.3.10.2. EPP Data or Address Read Cycle Timing Parameters
PARAMETER SYM. MIN. MAX. UNIT
WAIT Asserted to WRITE Deasserted
t14 t15 t17 t18 t19 t20 t21 t22
0 60 60 0 0 60 1 0
185 190 180
nS nS nS nS nS
Deasserted to WRITE Modified
WAIT Asserted to PD Hi-Z
Command Asserted to PD Valid Command Deasserted to PD Hi-Z
WAIT Deasserted to PD Drive WRITE Deasserted to Command
190
nS nS
PBDIR Set to Command
20
nS
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
EPP Data or Address Read Cycle Timing Parameters, continued
PARAMETER
SYM.
MIN.
MAX.
UNIT
PD Hi-Z to Command Asserted Asserted to Command Asserted
WAIT Deasserted to Command Deasserted
t23 t24 t25 t26 t27 t28 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24
0 0 60 10 0 0 40 0 10 40 0 0 0 0 60 0 0 0 60 0 60 0 0 60 1 0 0 0
30 195 180 12
nS nS nS nS nS S nS nS
Time out PD Valid to WAIT Deasserted PD Hi-Z to WAIT Deasserted Ax Valid to IOR Asserted IOCHRDY Deasserted to IOR Deasserted
IOR Deasserted to Ax Valid IOR Deasserted to IOW or IOR Asserted IOR Asserted to IOCHRDY Asserted
10
nS
24 75 40 85 160
nS nS S nS nS nS nS
PD Valid to SD Valid
IOR Deasserted to SD Hi-Z (Hold Time)
SD Valid to IOCHRDY Deasserted
WAIT Deasserted to IOCHRDY Deasserted
PD Hi-Z to PDBIR Set
WRITE Deasserted to IOR Asserted WAIT Asserted to WRITE Deasserted
185 190 50 180
nS nS nS nS nS nS
Deasserted to WRITE Modified
IOR Asserted to PD Hi-Z WAIT Asserted to PD Hi-Z
Command Asserted to PD Valid Command Deasserted to PD Hi-Z
WAIT Deasserted to PD Drive WRITE Deasserted to Command
190
nS nS
PBDIR Set to Command PD Hi-Z to Command Asserted Asserted to Command Asserted
20 30 195
nS nS nS
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
EPP Data or Address Read Cycle Timing Parameters, continued
PARAMETER
SYM.
MIN.
MAX.
UNIT
WAIT Deasserted to Command Deasserted
t25 t26 t27 t28
60 10 0 0
180 12
nS nS nS S
Time out PD Valid to WAIT Deasserted PD Hi-Z to WAIT Deasserted
21.3.10.3. EPP Data or Address Read Cycle (EPP Version 1.9)
EPP Data or Address Read Cycle (EPP Version 1.9)
t14 STB# / WRITE t15
t17 PD<0:7> t21 t23 t24 ADDRSTB
t18
t19
t20
t25
DATASTB t27 BUSY / WAIT t28
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
21.3.10.4. EPP Data or Address Read Cycle (EPP Version 1.7)
EPP Data or Address Read Cycle (EPP Version 1.7)
t14 STB# / WRITE t15
t17 PD<0:7> t21 t23 t24 ADDRSTB
t18
t19
t20
t25
DATASTB t27 BUSY / WAIT t28
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
21.3.10.5. EPP Data or Address Write Cycle Timing Parameters
PARAMETER SYM. MIN. MAX. UNIT
PBDIR Low to WRITE Asserted
WAIT Asserted to WRITE Asserted WAIT Asserted to WRITE Change WAIT Asserted to PD Invalid
t10 t11 t12 t14 t15 t17 t18 t19 t20 t21 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19
0 60 60 0 10 60 60 0 10 0 40 10 10 0 10 40 0 60 0 0 60 60 0 0 10 5 60 60 0 35 210 190 10 185 185 50 24 160 70 210 190 10 12 185 185
nS nS nS nS nS nS nS S S nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS S
PD Invalid to Command Asserted
WAIT Asserted to Command Asserted WAIT Deasserted to Command Deasserted
Command Asserted to WAIT Deasserted Time out Command Deasserted to WAIT Asserted Ax Valid to IOW Asserted SD Valid to Asserted
IOW Deasserted to Ax Invalid WAIT Deasserted to IOCHRDY Deasserted
Command Asserted to WAIT Deasserted
IOW Deasserted to IOW or IOR Asserted
IOCHRDY Deasserted to IOW Deasserted
WAIT Asserted to Command Asserted IOW Asserted to WAIT Asserted
PBDIR Low to WRITE Asserted
WAIT Asserted to WRITE Asserted WAIT Asserted to WRITE Change IOW Asserted to PD Valid WAIT Asserted to PD Invalid
PD Invalid to Command Asserted
IOW to Command Asserted WAIT Asserted to Command Asserted WAIT Deasserted to Command Deasserted
Command Asserted to WAIT Deasserted
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
EPP Data or Address Write Cycle Timing Parameters, continued
PARAMETER
SYM.
MIN.
MAX.
UNIT
Time out Command Deasserted to WAIT Asserted
IOW Deasserted to WRITE Deasserted and PD invalid WRITE to Command Asserted
t20 t21 t22 t16
10 0 0 5
12
S nS nS
35
nS
21.3.10.6. EPP Data or Address Write Cycle (EPP Version 1.9)
EPP Data or Address Write Cycle (EPP Version 1.9)
t11 t10 STB# / WRITE t12
t14 PD<0:7> t15 t16 t17 ADDRSTB t18
DATASTB t19 BUSY / WAIT t22 PBDIR t21
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
21.3.10.7. EPP Data or Address Write Cycle (EPP Version 1.7)
EPP Data or Address Write Cycle (EPP Version 1.7)
t11 t10 STB# / WRITE
PD<0:7> t15 t16 t17 DATAST t18
ADDRSTB t19 BUSY / WAIT
21.3.10.8. Parallel Port FIFO Timing Parameters
PARAMETER SYMBOL MIN. MAX. UNIT
DATA Valid to nSTROBE Active nSTROBE Active Pulse Width DATA Hold from nSTROBE Inactive BUSY Inactive to PD Inactive BUSY Inactive to nSTROBE Active nSTROBE Active to BUSY Active
t1 t2 t3 t4 t5 t6
600 600 450 80 680 500
nS nS nS nS nS nS
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
21.3.10.9. Parallel FIFO Timing
t4 t3
PD<0:7>
t1 t2 t5
STB#
t6
BUSY
21.3.10.10.
ECP Parallel Port Forward Timing Parameters
PARAMETER SYMBOL MIN. MAX. UNIT
nAUTOFD Valid to nSTROBE Asserted PD Valid to nSTROBE Asserted BUSY Deasserted to nAUTOFD Changed BUSY Deasserted to PD Changed nSTROBE Deasserted to BUSY Deasserted BUSY Deasserted to nSTROBE Asserted nSTROBE Asserted to BUSY Asserted BUSY Asserted to nSTROBE Deasserted
t1 t2 t3 t4 t5 t6 t7 t8
0 0 80 80 0 80 0 80
60 60 180 180 200 180
nS nS nS nS nS nS nS nS
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
21.3.10.11. ECP Parallel Port Forward Timing
t3
nAUTOFD
t4
PD<0:7>
t1 t2 t6 t8
STB#
t5 t7 t5
BUSY
21.3.10.12.
ECP Parallel Port Reverse Timing Parameters
PARAMETER SYMBOL MIN. MAX. UNIT
PD Valid to nACK Asserted nAUTOFD Deasserted to PD Changed nAUTOFD Asserted to nACK Asserted nAUTOFD Deasserted to nACK Deasserted nACK Deasserted to nAUTOFD Asserted PD Changed to nAUTOFD Deasserted
t1 t2 t3 t4 t5 t6
0 0 0 0 80 80 200 200
nS nS nS nS nS nS
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
21.3.10.13. ECP Parallel Port Reverse Timing
t2
PD<0:7>
t1 t3 t4
nACK
t5 t6 t5
nAUTOFD
21.3.11 KBC Timing Parameters
SYMBOL DESCRIPTION MIN. MAX. UNIT
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T19 T20 T21
Address Setup Time from WRB Address Setup Time from RDB WRB Strobe Width RDB Strobe Width Address Hold Time from WRB Address Hold Time from RDB Data Setup Time Data Hold Time Gate Delay Time from WRB RDB to Drive Data Delay RDB to Floating Data Delay Data Valid After Clock Falling (SEND) K/B Clock Period K/B Clock Pulse Width Data Valid Before Clock Falling (RECEIVE) K/B ACK After Finish Receiving Transmit Timeout Data Valid Hold Time Input Clock Period (6-16 Mhz)
0 0 20 20 0 0 50 0 10 0 20 10 4 20 2 0 63 167 30 40 20 4
nS nS nS nS nS nS nS nS nS nS nS S S S S S mS S nS
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
KBC Timing Parameters, continued
SYMBOL
DESCRIPTION
MIN.
MAX.
UNIT
T22 T23 T24 T25 T26 T27 T28 T29
Duration of CLK inactive Duration of CLK active Time from inactive CLK transition, used to time when the auxiliary device sample DATA Time of inhibit mode Time from rising edge of CLK to DATA transition Duration of CLK inactive Duration of CLK active Time from DATA transition to falling edge of CLK
30 30 5 100 5 30 30 5
50 50 25 300 T28-5 50 50 25
S S S S S S S S
21.3.11.1. Writing Cycle Timing
A2, CSB
T1
T3
T5
WRB
ACTIVE
T7 T8
D0 ~ D7 GA20 OUTPUT PORT
DATA IN
T9
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
21.3.11.2. Read Cycle Timing
A2, CSB AEN T2 RDB T4 ACTIVE T10 D0 ~ D7 T11 DATA OUT T6
21.3.11.3. Send Data to K/B
CLOCK (KCLK)
T14 T12 T13 T26
SERIAL DATA (KDAT)
START
D0
D1
D2
D3
D4
D5
D6
D7
P
STOP
21.3.11.4. Receive Data from K/B
CLOCK (KCLK)
T15 T14 T13
SERIAL DATA (T1)
START
D0
D1
D2
D3
D4
D5
D6
D7
P
STOP
T20
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
21.3.11.5. Input Clock
CLOCK
T21
21.3.11.6. Send Data to Mouse
MCLK
T25 T22 T23 T24
MDAT
START Bit
D0
D1
D2
D3
D4
D5
D6
D7
P
STOP Bit
21.3.11.7. Receive Data from Mouse
MCLK
T26 T29 T28 START D0 D1 D2 D3 D4 D5 D6 D7 P STOP Bit T27
MDAT
21.3.12
tWGO tSWP
GPIO Timing Parameters
PARAMETER MIN. MAX. UNIT
SYMBOL
Write data to GPIO update SWITCH pulse width 16
300(Note 1)
ns msec
Note: Refer to Microprocessor Interface Timing for Read Timing.
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
21.3.12.1. GPIO Write Timing
GPIO Write Timing diagram
A0 - A15
VALID
IOW
D0-7
VALID
GPIO 10-17 PREVIOUS STATE GPIO 20-25 tWGO VALID
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
21.4 LPC Timing
SYMBOL
DESCRIPTION
MIN.
MAX.
UNIT
t1 t2 t3 t4 t5 t6
Output Valid Delay Float Delay LAD[3:0] Setup Time LAD[3:0] Hold Time LFRAME# Setup Time LFRAME# Hold Time
4 4 14 0 12 0
11 11
nS nS nS nS nS nS
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
22. TOP MARKING SPECIFICATION
inbond
W83627DHG
606G9C28201234UB
1st line: Winbond logo 2nd line: part number: W83627DHG (Pb-free package) 3rd line: tracking code 606G9C28201234UB 606: packages made in '06, week 06 G: assembly house ID; G means GR, A means ASE, etc. 9: code version; 9 means code 009 C: IC revision; A means version A; B means version B, and C means version C 28201234: wafer production series lot number UB: Winbond internal use.
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
23. PACKAGE SPECIFICATION
Dimension in mm Dimension in inch
HE E
102 65
Symbol Min
Nom
0.35 2.72 0.20 0.15 14.00 20.00 0.50
Max
0.45 2.87 0.30 0.20 14.10 20.10
Min
0.010 0.101
Nom Max
0.014 0.107 0.018 0.113 0.012
103
64
D
HD
128
39
1
e
b
38
A1 A2 b c D E e HD HE L L1 y 0
c
0.25 2.57 0.10 0.10 13.90 19.90
0.004 0.008
0.004 0.006 0.008 0.547 0.551 0.555 0.791
0.783 0.787 0.020
17.00 23.00 0.65
17.20 23.20 0.80 1.60
17.40 23.40 0.95
0.669
0.677 0.685 0.921
0.905 0.913 0.025
0.031 0.037 0.063
0.08 0 7 0
0.003 7
Note:
1.Dimension D & E do not include interlead flash. 2.Dimension b does not include dambar protrusion/intrusion . 3.Controlling dimension : Millimeter 4.General appearance spec. should be based on final visual inspection spec. 5. PCB layout please use the "mm".
A A2 See Detail F Seating Plane A1 y
L L1 Detail F
128-pin (QFP)
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Publication Release Date: Aug, 22, 2007 Version 1.4
W83627DHG
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
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Publication Release Date: Aug, 22, 2007 Version 1.4

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